Sunwei Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56646 )
Change subject: mb/google/dedede/var/cappy2: Add usb port configruation ......................................................................
mb/google/dedede/var/cappy2: Add usb port configruation
This change adds fine-tuned USB2 PHY parameters for cappy2.
BUG=None TEST=Usb port work normally in cappy2
Signed-off-by: Sunwei Li lisunwei@huaqin.corp-partner.google.com Change-Id: Ib3bd8f963fe1a637b25608e98d28004ff24003c7 --- M src/mainboard/google/dedede/variants/cappy2/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/56646/1
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb index b11a417..eb8e2dd 100644 --- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb @@ -36,6 +36,31 @@ }, }"
+ # USB Port Configuration + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_16P9MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # WWAN + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Camera device domain 0 on device pci 15.0 on chip drivers/i2c/hid