Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43302 )
Change subject: soc/amd/picasso: Add support for RAM hash ......................................................................
soc/amd/picasso: Add support for RAM hash
This CL allocates a region in EARLY_DRAM to store the RAM hashes. It also introduces a hard coded memory map based on the current e820 map. In the future we could maybe automate the generate of the hash_ranges. Until now we will need to keep it updated.
To enable, add the following to your .config:
CONFIG_ENABLE_RAM_HASH=y
Hashing RAM from the SMM handler is pretty slow compared to trying it in bootblock. Not sure if the OS has reset the MTRRs.
Example of entering S3: coreboot-4.12-1163-gd9cc83a4ce58-dirty Tue Jul 7 21:34:13 UTC 2020 smm starting (log level: 8)...
SMI# #0 SMI#: SLP = 0x0c01 hash_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB ...
Example of exiting S3: Timestamp - ACPI wake jump: 36887335255 verify_ram: Start for_each_range: Processing range 0x1000 -> 0xa0000 Processed block 128: crc: 0x7f00c996. Remaining: 0 MiB Processed block 256: crc: 0x7f00c996. Remaining: 0 MiB Processed block 384: crc: 0x7f00c996. Remaining: 0 MiB Processed block 512: crc: 0x7f00c996. Remaining: 0 MiB for_each_range: Processing range 0x100000 -> 0x2000000 for_each_range: Processing range 0x22cd000 -> 0xcc50c000 Processed block 128: crc: 0x9a22c19c. Remaining: 3107 MiB Processed block 256: crc: 0x9a22c19c. Remaining: 2979 MiB Processed block 384: crc: 0x9a22c19c. Remaining: 2851 MiB Processed block 512: crc: 0x9a22c19c. Remaining: 2723 MiB Processed block 640: crc: 0x9a22c19c. Remaining: 2595 MiB Processed block 768: crc: 0x9a22c19c. Remaining: 2467 MiB Processed block 896: crc: 0x9a22c19c. Remaining: 2339 MiB Processed block 1024: crc: 0x9a22c19c. Remaining: 2211 MiB Processed block 1152: crc: 0x9a22c19c. Remaining: 2083 MiB Processed block 1280: crc: 0x9a22c19c. Remaining: 1955 MiB Processed block 1408: crc: 0x9a22c19c. Remaining: 1827 MiB Processed block 1536: crc: 0x9a22c19c. Remaining: 1699 MiB Processed block 1664: crc: 0x9a22c19c. Remaining: 1571 MiB Processed block 1792: crc: 0x9a22c19c. Remaining: 1443 MiB Processed block 1920: crc: 0x9a22c19c. Remaining: 1315 MiB Processed block 2048: crc: 0x9a22c19c. Remaining: 1187 MiB Processed block 2176: crc: 0x9a22c19c. Remaining: 1059 MiB Processed block 2304: crc: 0x9a22c19c. Remaining: 931 MiB Processed block 2432: crc: 0x9a22c19c. Remaining: 803 MiB Processed block 2560: crc: 0x9a22c19c. Remaining: 675 MiB Processed block 2688: crc: 0x9a22c19c. Remaining: 547 MiB Processed block 2816: crc: 0x9a22c19c. Remaining: 419 MiB Processed block 2944: crc: 0x9a22c19c. Remaining: 291 MiB Processed block 3072: crc: 0x9a22c19c. Remaining: 163 MiB Processed block 3200: crc: 0x9a22c19c. Remaining: 35 MiB verify_ram: Done
BUG=b:159081993 TEST=S3 suspend and resume on trembyle
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ia9b80044dd794ddfb0b661d517367259917cd944 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/ram_hash.c M src/soc/amd/picasso/smihandler.c 5 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43302/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fd2a205..2e7ce89 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,6 +57,7 @@ select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS + select HAS_RAM_HASH
config MEMLAYOUT_LD_FILE string @@ -174,6 +175,20 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86.
+config RAM_HASH_ADDR + hex + depends on ENABLE_RAM_HASH + default 0x21CD000 + help + Where in memory to store the hashes. + +config RAM_HASH_SIZE + hex + depends on ENABLE_RAM_HASH + default 0x100000 + help + Size of the RAM_HASH buffer. + config RAMBASE hex default 0x10000000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..679ee98 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -89,6 +89,9 @@ smm-y += smu.c smm-y += config.c
+ramstage-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c +smm-$(CONFIG_ENABLE_RAM_HASH) += ram_hash.c + CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..bb15263 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -89,6 +89,10 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif
+#if CONFIG(ENABLE_RAM_HASH) + REGION(hash_buffer, 0x21CD000, 1M, 4) +#endif + EARLY_RESERVED_DRAM_END(.)
RAMSTAGE(CONFIG_RAMBASE, 8M) diff --git a/src/soc/amd/picasso/ram_hash.c b/src/soc/amd/picasso/ram_hash.c new file mode 100644 index 0000000..c7f0be4 --- /dev/null +++ b/src/soc/amd/picasso/ram_hash.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <ram_hash.h> +#include <commonlib/bsd/helpers.h> + +struct hash_range mem_layout[] = { + { + .start = 0x1000, + .end = 0xa0000, + .block_size = 1 * KiB, + .diff = 1 + }, + { + .start = 0x100000, + .end = 0x2000000, + .block_size = 1 * MiB, + .diff = 0 + }, + { + .start = 0x22cd000, + .end = 0xcc50c000, + .block_size = 1 * MiB, + .diff = 0 + }, +}; + +void soc_hash_ram(void) +{ + hash_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} +void soc_verify_ram(void) +{ + verify_ram(mem_layout, ARRAY_SIZE(mem_layout)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..6832526 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <ram_hash.h> #include <cpu/x86/cache.h> #include <cpu/amd/amd64_save_state.h> #include <acpi/acpi.h> @@ -144,6 +145,13 @@ printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt);
+ /* + * Hash RAM as soon as we know we are entering S3 to catch any problems + * caused by the SMM handler, PSP, or SMU. + */ + if (slp_typ == ACPI_S3) + soc_hash_ram(); + /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ);