Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59862 )
Change subject: mb/google/brya:[TEST_ONLY] Run Mem frequency @ lowest Speed ......................................................................
mb/google/brya:[TEST_ONLY] Run Mem frequency @ lowest Speed
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: Ibbc591aff89e166bf90c0cec8bd308f8ea5a47dd --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59862/1
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 47e81d8..365761a 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -24,6 +24,7 @@ # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" register "gpio_pm[COMM_0]" = "0" register "gpio_pm[COMM_1]" = "0" @@ -40,6 +41,8 @@ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + + register "MaxDramSpeed" = "1067" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |