Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62080 )
Change subject: sb/amd/sb700: Strip the code just to be buildable ......................................................................
sb/amd/sb700: Strip the code just to be buildable
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5624397b6d9215f575f73305bb51ac1409558020 --- M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/Makefile.inc M src/southbridge/amd/sb700/fadt.c D src/southbridge/amd/sb700/ramtop.c 4 files changed, 9 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/62080/1
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 58dc75a..7573ebe 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,6 +25,9 @@ select SMBUS_HAS_AUX_CHANNELS select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI bool "Enable high speed SPI clock" diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 0a20a8c..6d4f516 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,27 +1,13 @@ ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB700),y)
-ramstage-y += sb700.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += smbus.c -ramstage-y += sm.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += hda.c -ramstage-y += pci.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c romstage-y += reset.c ramstage-y += reset.c -ramstage-y += spi.c
bootblock-y += enable_usbdebug.c romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c
-romstage-y += early_setup.c -romstage-y += smbus.c - -romstage-y += ramtop.c -ramstage-y += ramtop.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-y += sb700.c
endif diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index c81e644..03ee3c7f 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -20,31 +20,18 @@
#include <string.h> #include <console/console.h> -#include <arch/acpi.h> +#include <acpi/acpi.h> #include <device/device.h> -#include <cpu/amd/powernow.h> #include <version.h>
#include "sb700.h"
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_fill_fadt(acpi_fadt_t * fadt) { acpi_header_t *header = &(fadt->header);
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB700_ACPI_IO_BASE);
- /* Prepare the header */ - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -94,10 +81,6 @@ fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; @@ -155,8 +138,8 @@ fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0;
- if (CONFIG(CPU_AMD_MODEL_10XXX)) - amd_powernow_update_fadt(fadt); + // if (CONFIG(CPU_AMD_MODEL_10XXX)) + // amd_powernow_update_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/ramtop.c deleted file mode 100644 index 4d26121..0000000 --- a/src/southbridge/amd/sb700/ramtop.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include "sb700.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp; - tmp = inw(ACPI_PM1_CNT_BLK); - return ((tmp & (7 << 10)) >> 10); -} - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xfc, i; - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xfc, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -}