[coreboot-gerrit] Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definiti...

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 )

Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
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Patch Set 28:

(2 comments)

https://review.coreboot.org/c/coreboot/+/35546/27/src/soc/intel/cannonlake/i... 
File src/soc/intel/cannonlake/include/soc/me.h:

https://review.coreboot.org/c/coreboot/+/35546/27/src/soc/intel/cannonlake/i... 
PS27, Line 34: 		u32 reserved0: 1;
> Yes, it's a enhanced debug mode for CML, and a reserved field for WHL. I updated the structure.

Done

https://review.coreboot.org/c/coreboot/+/35546/27/src/soc/intel/common/block... 
File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/35546/27/src/soc/intel/common/block... 
PS27, Line 253: union me_hfsts1 hfs1;
              : 	hfs1.data = me_read_config32(PCI_ME_HFSTS1);
              : 	if (hfs1.fields.operation_mode == ME_HFS1_COM_NORMAL)
              : 		return true;
              : 	return false;
> Implemented as above, done.

Done