Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35521 )
Change subject: [WIP] intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35521/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pci.c:
https://review.coreboot.org/c/coreboot/+/35521/1/src/southbridge/intel/bd82x... PS1, Line 78: dev->command |= PCI_COMMAND_IO;
Hmm.. I think specs says VGA IO decode is enabled regardless of PCI_COMMAND_IO bit.
Yeah, now that I found cardbus specs, I think both IO and MEMORY should be set in PCI_COMMAND.
https://review.coreboot.org/c/coreboot/+/35521/1/src/southbridge/intel/bd82x... PS1, Line 86: ich_pci_dev_enable_resources(dev); I am also staring at this comment, looking into CB:31987 that seems to be related. Prior to that commit, I think the intention was to avoid making duplicate calls to .set_subsystem. And currently bd82x6x and i82801gx do not make the call at all...?
Those SSID registers are sometimes write-once. I'll make a commit to make this look like i82801ix/pci.c and wait for feedback.