[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix

[Ronak Kanabar (Code Review)]

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31154

Change subject: soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix
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soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.

Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/cannonlake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31154/1

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 4dab334..f9f3e96 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -121,13 +121,13 @@
    },
 };

-static int cstate_set_s0ix[] = {
+static int cstate_set_non_s0ix[] = {
    C_STATE_C1E,
    C_STATE_C6_LONG_LAT,
    C_STATE_C7S_LONG_LAT
 };

-static int cstate_set_non_s0ix[] = {
+static int cstate_set_s0ix[] = {
    C_STATE_C1E,
    C_STATE_C7S_LONG_LAT,
    C_STATE_C10