[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update pci dev definition

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )

Change subject: soc/intel/tigerlake: Update pci dev definition
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... 
PS12, Line 105: #define PCH_DEV_SLOT_STORAGE	0x1A
Why is this getting removed? Atleast as per Jasperlake EDS, EMMC is present on this PCH Device ID and I believe Jasperlake is going to share this PCI BDF definition with TGL.