[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: add 0xcf9 reset

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )

Change subject: soc/amd/cezanne: add 0xcf9 reset
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c 
File src/soc/amd/cezanne/reset.c:

https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... 
PS3, Line 49: void chipset_handle_reset(uint32_t status)
> Hmm, how did this build correctly?  This is prototyped in src/drivers/intel/fsp2_0/include/fsp/util. […]

https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/include... has the function prototype. factoring that out to the common code that only gets added when the fsp is already integrated sounds like a good idea though