[coreboot-gerrit] [S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree

[Felix Held (Code Review)]

Attention is currently required from: Angel Pons.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79169?usp=email )

Change subject: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
......................................................................

sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree

Since the PCI bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the PCI bridge device operations to the PCI
device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held 
Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a
---
M src/northbridge/intel/sandybridge/chipset.cb
M src/southbridge/intel/bd82x6x/pci.c
2 files changed, 2 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/79169/1

diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index f11fd2f..29e9d7f 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -36,7 +36,7 @@
    		device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #7
    		device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #8
    		device pci 1d.0 alias ehci1 off end      # USB2 EHCI #1
-			device pci 1e.0 alias pci_bridge off end # PCI bridge
+			device pci 1e.0 alias pci_bridge off ops bd82x6x_pci_bridge_ops end
    		device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end
    		device pci 1f.2 alias sata1 off end      # SATA Controller 1
    		device pci 1f.3 alias smbus on ops bd82x6x_smbus_ops end
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 382506b..2294421 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -35,7 +35,7 @@
    pci_write_config16(dev, SECSTS, reg16);
 }

-static struct device_operations device_ops = {
+struct device_operations bd82x6x_pci_bridge_ops = {
    .read_resources		= pci_bus_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,
@@ -43,15 +43,3 @@
    .scan_bus		= pci_scan_bridge,
    .ops_pci		= &pci_dev_ops_pci,
 };
-
-static const unsigned short pci_device_ids[] = {
-	0x2448, /* Mobile */
-	0x244e, /* Desktop */
-	0
-};
-
-static const struct pci_driver pch_pci __pci_driver = {
-	.ops		= &device_ops,
-	.vendor		= PCI_VID_INTEL,
-	.devices	= pci_device_ids,
-};