[coreboot-gerrit] [M] Change in coreboot[master]: mb/google/brya/var/constitution: Add SOLDERDOWN support

[Morris Hsu (Code Review)]

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72775 )

Change subject: mb/google/brya/var/constitution: Add SOLDERDOWN support
......................................................................

mb/google/brya/var/constitution: Add SOLDERDOWN support

Constitution will use SOLDERDOWN. Add memory.c to override baseboard.

BUG=b:267539938
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a

Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/constitution/Makefile.inc
A src/mainboard/google/brya/variants/constitution/memory.c
4 files changed, 122 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/72775/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index c947ce8..1e63406 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -53,7 +53,7 @@
    select BOARD_ROMSIZE_KB_32768
    select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
    select HAVE_SLP_S0_GATE
-	select MEMORY_SODIMM
+	select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION
    select RT8168_GEN_ACPI_POWER_RESOURCE
    select RT8168_GET_MAC_FROM_VPD
    select RT8168_SET_LED_MODE
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 5c393b7..452f57b 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -335,3 +335,4 @@
 config BOARD_GOOGLE_CONSTITUTION
    bool "->  Constitution"
    select BOARD_GOOGLE_BASEBOARD_BRASK
+	select MEMORY_SOLDERDOWN
diff --git a/src/mainboard/google/brya/variants/constitution/Makefile.inc b/src/mainboard/google/brya/variants/constitution/Makefile.inc
new file mode 100644
index 0000000..c44e4f0
--- /dev/null
+++ b/src/mainboard/google/brya/variants/constitution/Makefile.inc
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+romstage-y += memory.c
diff --git a/src/mainboard/google/brya/variants/constitution/memory.c b/src/mainboard/google/brya/variants/constitution/memory.c
new file mode 100644
index 0000000..436353c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/constitution/memory.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  3,  0,  2,  1,  4,  6,  5,  7, },
+			.dq1 = {  12, 13, 14, 15, 8,  9,  10, 11, },//check DDR_A_DQ0,DDR_A_DQ1
+		},
+		.ddr1 = {
+			.dq0 = { 13, 14, 11, 12,  10, 8, 15,  9, },
+			.dq1 = {  5,  2,  4,  3,  1,  6,  0,  7, },//check DDR_A_DQ2,DDR_A_DQ3
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  7,  6,  5,  4, },
+			.dq1 = { 12,  13, 14, 15, 8,  9, 10, 11, },//check DDR_A_DQ4,DDR_A_DQ5
+		},
+		.ddr3 = {
+			.dq0 = { 13, 14, 12, 15, 11,  9,  8, 10, },
+			.dq1 = {  5,  2,  1,  4,  7,  0,  3,  6, },//check DDR_A_DQ6,DDR_A_DQ7
+		},
+		.ddr4 = {
+			.dq0 = { 11, 10,  8,  9, 14, 15, 13, 12, },
+			.dq1 = {  3,  0,  2,  1,  5,  4,  6,  7, },//check DDR_B_DQ0,DDR_B_DQ1
+		},
+		.ddr5 = {
+			.dq0 = { 11, 15, 13, 12, 10,  9, 14,  8, },
+			.dq1 = {  3,  0,  2,  1,  6,  7,  5,  4, },//check DDR_B_DQ2,DDR_B_DQ3
+		},
+		.ddr6 = {
+			.dq0 = { 11, 13, 10, 12, 15,  9, 14,  8, },
+			.dq1 = {  4,  3,  5,  2,  7,  0,  1,  6, },//check DDR_B_DQ4,DDR_B_DQ5
+		},
+		.ddr7 = {
+			.dq0 = { 12, 13, 15, 14, 11,  9, 10,  8, },
+			.dq1 = {  4,  5,  1,  2,  6,  3,  0,  7, },//check DDR_B_DQ6,DDR_B_DQ7
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },//check
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },//check
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },//check
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },//check
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },//check
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },//check
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },//check
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 },//check
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_F16
+	 * GPIO_MEM_CONFIG_1	GPP_F12
+	 * GPIO_MEM_CONFIG_2	GPP_F13
+	 * GPIO_MEM_CONFIG_3	GPP_F15
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_F16,
+		GPP_F12,
+		GPP_F13,
+		GPP_F15,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_F11 */
+	return gpio_get(GPP_F11);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}