Attention is currently required from: Furquan Shaikh, Paul Menzel, Alan Huang. Alan Huang has uploaded a new patch set (#14) to the change originally created by David Wu. ( https://review.coreboot.org/c/coreboot/+/56539 )
Change subject: mb/google/brya: Enable DDR4 SODIMM for brask ......................................................................
mb/google/brya: Enable DDR4 SODIMM for brask
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs.
Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask.
Add a new Kconfig item FMDFILE and a new fmd file for brask which needs a RW_SPD_CACHE section.
The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types.
BUG=b:194055762 BRANCH=None TEST=build pass
Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang alan-huang@quanta.corp-partner.google.com --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/chromeos-brask.fmd R src/mainboard/google/brya/chromeos-brya.fmd R src/mainboard/google/brya/romstage.c M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb A src/mainboard/google/brya/variants/baseboard/brask/memory.c M src/mainboard/google/brya/variants/baseboard/brya/memory.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 10 files changed, 120 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56539/14