[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Configure GPIOs again after FSP-S is done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31236

Change subject: mb/google/hatch: Configure GPIOs again after FSP-S is done
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mb/google/hatch: Configure GPIOs again after FSP-S is done

FSP-S is currently configuring GPIOs that it should not. This results
in issues like host unable to receive TPM interrupts as the pad for
the interrupt is re-configured as something else.

Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log.

Change-Id: Ib197529a730f0142152c94ddf4a2b005bae123f5
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/hatch/ramstage.c
1 file changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31236/1

diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index b8e80e7..e2fe048 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -20,7 +20,7 @@
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+static void mainboard_configure_gpios(void)
 {
    const struct pad_config *gpio_table;
    size_t num_gpios;
@@ -29,10 +29,22 @@
    gpio_configure_pads(gpio_table, num_gpios);
 }

+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	mainboard_configure_gpios();
+}
+
+static void mainboard_init(struct device *dev)
+{
+	/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
+	mainboard_configure_gpios();
+}
+
 static void mainboard_enable(struct device *dev)
 {
    mainboard_ec_init();

+	dev->ops->init = mainboard_init;
    dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }