Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64027 )
Change subject: mb/google/brya/var/crota: setting for codec reset pin ......................................................................
mb/google/brya/var/crota: setting for codec reset pin
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing.
BUG=b:230074351 BRANCH=none TEST=build coreboot without error
Signed-off-by: Terry Chen terry_chen@wistron.corp-partner.google.com Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/crota/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index a546455..35803a0 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -22,8 +22,8 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + /* B15 : PROC_GP3 ==> AUD_RST_L */ + PAD_CFG_GPO(GPP_B15, 1, PWROK),
/* C3 : GPP_C3 ==> SML0_SMBCLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.