Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38387 )
Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Update SA bit fields as per EDS ......................................................................
soc/intel/{apl,cnl,icl,skl,tgl}: Update SA bit fields as per EDS
This patch updates system agent related registers bit definitions as per EDS.
For an example: As per EDS MCHBAR register base is between bit 16-38 but coreboot programming was not align with EDS previously.
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/romstage/systemagent.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/romstage/systemagent.c M src/soc/intel/icelake/systemagent.c M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/romstage/systemagent.c M src/soc/intel/tigerlake/systemagent.c 16 files changed, 88 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38387/1
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 258f4ff..44eb453 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -79,7 +79,7 @@ static void soc_early_romstage_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, };
/* Set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index fd91082..f51595f 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -36,8 +36,8 @@ { static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + "PCIEXBAR", true }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, };
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index 3bda9e8..ed86a99 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -53,14 +53,14 @@ #if CONFIG(SOC_INTEL_COFFEELAKE) || CONFIG(SOC_INTEL_WHISKEYLAKE) \ || CONFIG(SOC_INTEL_COMETLAKE) static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR", true }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR", true }, }; #else static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR", true }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR", true }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR", true }, }; #endif
diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c index 61db22e..0e50c12 100644 --- a/src/soc/intel/cannonlake/romstage/systemagent.c +++ b/src/soc/intel/cannonlake/romstage/systemagent.c @@ -24,14 +24,14 @@ void systemagent_early_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, };
static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, };
/* Set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 3f01f14..84513a0 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -35,12 +35,12 @@ { static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + "PCIEXBAR", true }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with @@ -51,7 +51,7 @@ * under this device space. */ { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, + "PMCBAR", true }, };
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index d271dda..ab50942 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -31,23 +31,23 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ - , 14, - MHBR, 17, /* MCHBAR [31:15] */ + , 15, + MHBR, 23, /* MCHBAR [38:16] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + , 25, + PXBR, 11, /* PCI Express BAR [38:28] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */
Offset (0xa0), TOM, 64, /* Top of Used Memory */ @@ -220,7 +220,7 @@ /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, Local0) + ShiftLeft (_SB.PCI0.MCHC.MHBR, 16, Local0) Return (Local0) }
@@ -234,7 +234,7 @@ /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) + ShiftLeft (_SB.PCI0.MCHC.PXBR, 28, Local0) Return (Local0) }
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index c605958..1d69e68 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -43,15 +43,17 @@ * Fixed MMIO range * INDEX = Either PCI configuration space registers or MMIO offsets * mapped from REG. - * BASE = 32 bit Address. + * BASE = Address. * SIZE = base length * DESCRIPTION = Name of the register/offset. + * IS_64_BIT = If registers/offset is 64 bit. */ struct sa_mmio_descriptor { unsigned int index; uintptr_t base; size_t size; const char *description; + bool is_64_bit; };
/* API to set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index d6f129d..8697dd5 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -71,12 +71,18 @@ int i;
for (i = 0; i < count; i++) { - uintptr_t base; + uint64_t base = 0; unsigned int index; + bool is64bit = fixed_set_resources[i].is_64_bit;
index = fixed_set_resources[i].index; + /* Check if PCI BAR already enabled */ - base = pci_read_config32(SA_DEV_ROOT, index); + if (is64bit) { + base = pci_read_config32(SA_DEV_ROOT, index + 4); + base <<= 32; + } + base |= pci_read_config32(SA_DEV_ROOT, index);
/* If enabled don't program it. */ if (base & 0x1) @@ -85,6 +91,9 @@ base = fixed_set_resources[i].base;
pci_write_config32(SA_DEV_ROOT, index, base | 1); + if (is64bit) { + pci_write_config32(SA_DEV_ROOT, index + 4, base >> 32); + } } }
diff --git a/src/soc/intel/icelake/romstage/systemagent.c b/src/soc/intel/icelake/romstage/systemagent.c index fc046a6..cea38a1 100644 --- a/src/soc/intel/icelake/romstage/systemagent.c +++ b/src/soc/intel/icelake/romstage/systemagent.c @@ -22,14 +22,14 @@ void systemagent_early_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, };
static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, };
/* Set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c index 930e78e..e57f2e8 100644 --- a/src/soc/intel/icelake/systemagent.c +++ b/src/soc/intel/icelake/systemagent.c @@ -29,12 +29,12 @@ { static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + "PCIEXBAR", true }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with @@ -45,7 +45,7 @@ * under this device space. */ { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, + "PMCBAR", true }, };
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 89380aa..ca79090 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -30,23 +30,23 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + , 25, + PXBR, 11, /* PCI Express BAR [38:28] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */ MEBA, 64, @@ -244,7 +244,7 @@ /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) + ShiftLeft (_SB.PCI0.MCHC.PXBR, 28, Local0) Return (Local0) }
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 91209c8..bf0acc2 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -52,14 +52,16 @@ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, - "GFXVTBAR" + "GFXVTBAR", + true };
static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, - "VTVC0BAR" + "VTVC0BAR", + true };
/* Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET */ diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index e1272a1..1316b5a 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -52,14 +52,14 @@ void systemagent_early_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, };
static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { - { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, };
/* Set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f..a9168f1 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -46,12 +46,12 @@
static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + "PCIEXBAR", true }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, + { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, }; const struct soc_intel_skylake_config *const config = config_of(dev);
diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c index 183089e..db721c3 100644 --- a/src/soc/intel/tigerlake/romstage/systemagent.c +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -27,14 +27,14 @@ void systemagent_early_init(void) { static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, };
static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, };
/* Set Fixed MMIO address into PCI configuration space */ diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 9c8f645..e0065e0 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -35,12 +35,12 @@ { static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, - { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, - { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, - { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + "PCIEXBAR", true }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR", true }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR", true }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR", true }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR", true }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR", true }, /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with @@ -51,7 +51,7 @@ * under this device space. */ { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, - "PMCBAR" }, + "PMCBAR", true }, };
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,