EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... PS20, Line 361: inline
static inline
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
@Subrata, could you help explain PEG a little bit?
Done
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... PS20, Line 148: pcie_rp_init
nit: I think it would be good to align this one more tab or basically move this to the previous line […]
Done