Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35150 )
Change subject: soc/mediatek: Fix USB enumeration issue ......................................................................
soc/mediatek: Fix USB enumeration issue
Some USB3.0 devices are failed to enumerate after USB reset, and xhci port status register show device is disconnected. After measure USB signal, we can find usb disconnect threshold is lower and disconnect event is triggered unexpectedly.
USB designer suggest to change discth to 15.
BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage
Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu changqi.hu@mediatek.com --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/1
diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h old mode 100644 new mode 100755 index 8a36c6a..22704e7 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -70,6 +70,8 @@ #define PA6_RG_U2_ISO_EN (0x1 << 31) #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_DISCTH (0xf << 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH (0xf << 0) #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)
diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c old mode 100644 new mode 100755 index dcb9307..f5263fb --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -76,6 +76,10 @@ /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + /*Set USB 2.0 disconnect threshold*/ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); }
static void u3phy_power_on(void)