Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51547 )
Change subject: mb/google/guybrush: Add eSPI GPIO back to init table ......................................................................
mb/google/guybrush: Add eSPI GPIO back to init table
GPIOs should be configured in ramstage even if they are configured in an earlier stage.
BUG=b:180721208
Signed-off-by: Mathew King mathewk@chromium.org Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/51547/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 9b8df52..1cd8c23 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -108,7 +108,14 @@ /* CLK_REQ0_L */ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), /* GPIO_93 - GPIO_103: Not available */ - /* GPIO_104 - GPIO_108: eSPI configured in early stage */ + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* RAM_ID_0 / DEV_BEEP_EN */ PAD_GPI(GPIO_109, PULL_NONE), /* GPIO_110 - GPIO_112: Not available */