[coreboot-gerrit] Change in coreboot[master]: [TESTME/RFC] mb/google/kahlee: move SMI/SCI GPIO setup to ramstage

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48608 )

Change subject: [TESTME/RFC] mb/google/kahlee: move SMI/SCI GPIO setup to ramstage
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[TESTME/RFC] mb/google/kahlee: move SMI/SCI GPIO setup to ramstage

SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.

BUG=b:175386410
TEST=UNTESTED

Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held 
---
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
1 file changed, 15 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48608/1

diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 59d7631..8628074 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -15,8 +15,8 @@
    /* GPIO_4 - EN_PP3300_WLAN */
    PAD_GPO(GPIO_4, HIGH),

-	/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
-	PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),
+	/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI gets configured in ramstage */
+	PAD_GPI(GPIO_6, PULL_UP),

/* GPIO_9 - H1_PCH_INT_ODL */
    PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),
@@ -24,11 +24,11 @@
    /* GPIO_15 - EC_IN_RW_OD */
    PAD_GPI(GPIO_15, PULL_UP),

-	/* GPIO_22 - EC_SCI_ODL, SCI */
-	PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
+	/* GPIO_22 - EC_SCI_ODL, SCI gets configured in ramstage */
+	PAD_GPI(GPIO_22, PULL_UP),

-	/* GPIO_24 - EC_PCH_WAKE_L, SCI */
-	PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+	/* GPIO_24 - EC_PCH_WAKE_L, SCI gets configured in ramstage */
+	PAD_GPI(GPIO_24, PULL_UP),

/* GPIO_26 - APU_PCIE_RST_L */
    PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
@@ -90,6 +90,9 @@
    /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
    PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW),

+	/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
+	PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),
+
    /* GPIO_7 - APU_PWROK_OD (currently not used) */
    PAD_GPI(GPIO_7, PULL_UP),

@@ -129,6 +132,12 @@
    /* GPIO_21 - APU_PEN_INT_ODL, SCI */
    PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW),

+	/* GPIO_22 - EC_SCI_ODL, SCI */
+	PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
+
+	/* GPIO_24 - EC_PCH_WAKE_L, SCI */
+	PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+
    /* GPIO_25 - SD_CD */
    PAD_NF(GPIO_25, SD0_CD, PULL_UP),