Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46419 )
Change subject: mb/intel/adlrvp: Enable PCIE RP11 for optane ......................................................................
Patch Set 1: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/46419/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46419/1//COMMIT_MSG@8 PS1, Line 8: So, if I understand correctly:
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width.
If I'm not mistaken, could you please mention so in the commit message?
https://review.coreboot.org/c/coreboot/+/46419/1//COMMIT_MSG@9 PS1, Line 9: config nit: add `:` at the end
https://review.coreboot.org/c/coreboot/+/46419/1//COMMIT_MSG@13 PS1, Line 13: Note: These two devices are sharing CLK PINs. This is because they use the same M.2 slot, right?