[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure RP setting

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40262 )

Change subject: soc/intel/tigerlake: Configure RP setting
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40262/3/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/40262/3/src/soc/intel/tigerlake/fsp... 
PS3, Line 128: 		params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i];
> We still need to set it as FSP default value is LTR disabled but we want to enable LTR by default(wi […]

Aah I see. In that case, I think we should just use the config for enable. It is confusing that some parameters for PCIe are positive and others are negative. Also, on previous Intel platforms, it looks like we are already using PcieRpLtrEnable[] that the mainboard sets. It would be good to be consistent.