Hello HAOUAS Elyes,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38877
to review the following change.
Change subject: [TESTME]mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK ......................................................................
[TESTME]mb/amd/thatcher: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I948eeaaeb7975561fffc1218c70dba6a784101fe --- M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/Kconfig.name M src/mainboard/amd/thatcher/Makefile.inc A src/mainboard/amd/thatcher/bootblock.c D src/mainboard/amd/thatcher/romstage.c 5 files changed, 38 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38877/1
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e556592..e1c5aee 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. #
-config BOARD_AMD_THATCHER - def_bool n - if BOARD_AMD_THATCHER
config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/thatcher/Kconfig.name b/src/mainboard/amd/thatcher/Kconfig.name index b57bdb9..aff5246 100644 --- a/src/mainboard/amd/thatcher/Kconfig.name +++ b/src/mainboard/amd/thatcher/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_THATCHER -# bool"Thatcher" +config BOARD_AMD_THATCHER + bool "Thatcher" diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c new file mode 100644 index 0000000..d251025 --- /dev/null +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) + +void bootblock_mainboard_early_init(void) +{ + post_code(0x30); + post_code(0x31); + + gpio_100_write8(0x1, 0x98); + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c deleted file mode 100644 index dff516c..0000000 --- a/src/mainboard/amd/thatcher/romstage.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <amdblocks/acpimmio.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/smsc/lpc47n217/lpc47n217.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u8 byte; - pci_devfn_t dev; - - /* Set LPC decode enables. */ - dev = PCI_DEV(0, 0x14, 3); - - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - post_code(0x30); - /* For serial port. */ - pci_write_config32(dev, 0x44, 0xff03ffd5); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - pm_io_write8(0x24, 1); - pm_io_write8(0xea, 1); - gpio_100_write8(0x1, 0x98); -}