James has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39021 )
Change subject: nb/intel/snb: Add PCI routing table for PEG root ports ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@9 PS1, Line 9: Previously the PRTs were defined in southbridge code (#13612), but this
Please at least add the commit message summary of the referenced commit/change-set. […]
Thanks, noted.
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@18 PS1, Line 18: > snd_hda_intel 0000:01:00.1: PCI INT B: no GSI
Instead of a (Markdown) citation, make it a code block by indenting it with 4 spaces.
Thanks, noted.
https://review.coreboot.org/c/coreboot/+/39021/1//COMMIT_MSG@20 PS1, Line 20: Tested with GIGABYTE P67A-UD3R (#31363) with Radeon HD 5670.
Tested with MSI (i.e. only tested that the warning goes away) or […]
nomsi gives the same results as with MSI. HDMI audio works as tested with speaker-test, although in any case, linux produces a warning "IRQ timing workaround is activated for card #1. Suggest a bigger bdl_pos_adj", even under OEM firmware.
https://review.coreboot.org/c/coreboot/+/39021/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/acpi/peg.asl:
https://review.coreboot.org/c/coreboot/+/39021/1/src/northbridge/intel/sandy... PS1, Line 137: Package() { 0x0000ffff, 0, 0, 16 },
In my vendor DSDT (H77 chipset), this device' table starts with 19. […]
Yes, I would avoid changing things if in doubt. I've only tested the PEG10 slot so far, and I don't have the capability to test PEG11, PEG12 or PEG60.