Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74518?usp=email )
(
4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region ......................................................................
soc/intel/jasperlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.
Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable).
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com --- M src/soc/intel/jasperlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 660b24a..4ecec60 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -73,7 +73,8 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP
config DCACHE_RAM_BASE default 0xfef00000