[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Fix TSEG size computation

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30932 )

Change subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation
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Patch Set 1:

(2 comments)

https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... 
File src/soc/intel/fsp_broadwell_de/smmrelocate.c:

https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... 
PS1, Line 229: + 1 * MiB;
> Wait a moment... […]

As the lower address bits are don't care, you decode all addresses in range [0x00000-0xfffff], which are 1 Meg in total.

https://review.coreboot.org/#/c/30932/1/src/soc/intel/fsp_broadwell_de/smmre... 
PS1, Line 241: 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
             : 	params->smrr_base.hi = 0;
             : 	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) |
             : 					MTRR_PHYS_MASK_VALID;
             : 	params->smrr_mask.hi = 0;
> from my experience it is likely that writing to SMRR hangs the system because base is not aligned to […]

The hang I experience is at a later point. I need to check the BWG, but it looks like 1 MiB alignment works just fine.