Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6811
-gerrit
commit 67645217a2f18fddcecd579a65c04ca32039e0ea Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Aug 31 02:21:43 2014 +0200
sch: Switch to collaborative ACPI
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 156 +------------------------- src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/intel/sch/acpi.c | 11 ++ src/northbridge/intel/sch/northbridge.c | 1 + src/northbridge/intel/sch/sch.h | 2 + src/southbridge/intel/sch/acpi/globalnvs.asl | 4 +- src/southbridge/intel/sch/lpc.c | 24 ++++ src/southbridge/intel/sch/nvs.h | 2 + 8 files changed, 44 insertions(+), 157 deletions(-)
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index ae7239b..4dcda79 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -29,14 +29,9 @@ #include <device/pci_ids.h> #include <cpu/x86/msr.h>
-extern const unsigned char AmlCode[]; -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif - #include "southbridge/intel/sch/nvs.h"
-static void acpi_create_gnvs(global_nvs_t * gnvs) +void acpi_create_gnvs(global_nvs_t * gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; @@ -75,13 +70,6 @@ unsigned long acpi_fill_madt(unsigned long current) return current; }
-unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long)(acpigen_get_current()); -} - unsigned long acpi_fill_slit(unsigned long current) { /* Not implemented. */ @@ -93,145 +81,3 @@ unsigned long acpi_fill_srat(unsigned long current) /* No NUMA, no SRAT */ return current; } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif - acpi_header_t *ssdt; - acpi_header_t *dsdt; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - ALIGN_CURRENT; - - /* Pack GNVS into the ACPI table area */ - for (i = 0; i < dsdt->length; i++) { - if (*(u32 *) (((u32) dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", - i, current); - *(u32 *) (((u32) dsdt) + i) = current; // 0x92 bytes - break; - } - } - - /* And fill it */ - acpi_create_gnvs((global_nvs_t *) current); - - current += 0x100; - ALIGN_CURRENT; - - /* And tell SMI about it */ - smm_setup_structures((void *)current, NULL, NULL); - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *) current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *) current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index f87afdf..b8dad72 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_SCH bool select MMCONF_SUPPORT + select PER_DEVICE_ACPI_TABLES
if NORTHBRIDGE_INTEL_SCH
diff --git a/src/northbridge/intel/sch/acpi.c b/src/northbridge/intel/sch/acpi.c index 6dd495f..34a6706 100644 --- a/src/northbridge/intel/sch/acpi.c +++ b/src/northbridge/intel/sch/acpi.c @@ -25,6 +25,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "sch.h"
unsigned long acpi_fill_mcfg(unsigned long current) { @@ -72,3 +76,10 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif return current; } + +unsigned long northbridge_acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 0bbf91b..ba7830b 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -281,6 +281,7 @@ static struct device_operations mc_ops = { #if CONFIG_HAVE_ACPI_RESUME .init = northbridge_init, #endif + .acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator, .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 5700842..19a1a40 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -25,6 +25,8 @@ int sch_port_access_read(int port, int reg, int bytes); void sch_port_access_write(int port, int reg, int bytes, long data); void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); +unsigned long northbridge_acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id);
/* Southbridge IO BARs */ /* TODO Make sure these don't get changed by stage2 */ diff --git a/src/southbridge/intel/sch/acpi/globalnvs.asl b/src/southbridge/intel/sch/acpi/globalnvs.asl index 5ac1c83..7db71f9 100644 --- a/src/southbridge/intel/sch/acpi/globalnvs.asl +++ b/src/southbridge/intel/sch/acpi/globalnvs.asl @@ -30,8 +30,8 @@ Name(\DSEN, 1) // Display Output Switching Enable * we have to fix it up in coreboot's ACPI creation phase. */
- -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index 08f4162..804f73d 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -24,6 +24,9 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <cbmem.h> +#include "nvs.h" #include "chip.h"
/* SCH LPC defines */ @@ -182,6 +185,25 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
+static unsigned long southbridge_fill_ssdt(unsigned long current, const char *oem_table_id) +{ + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + + if (gnvs) { + int scopelen; + acpi_create_gnvs(gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to SSDT. */ + scopelen = acpigen_write_scope("\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); + } + + return (unsigned long) (acpigen_get_current()); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -190,6 +212,8 @@ static struct device_operations device_ops = { .read_resources = sch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &pci_ops, diff --git a/src/southbridge/intel/sch/nvs.h b/src/southbridge/intel/sch/nvs.h index 14f0ad3..c987d92 100644 --- a/src/southbridge/intel/sch/nvs.h +++ b/src/southbridge/intel/sch/nvs.h @@ -135,3 +135,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +void acpi_create_gnvs(global_nvs_t * gnvs);