[coreboot-gerrit] Change in coreboot[master]: southbridge/nvidia: Remove spaces before/after parenthesis

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25879

Change subject: southbridge/nvidia: Remove spaces before/after parenthesis
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southbridge/nvidia: Remove spaces before/after parenthesis

Change-Id: I94a87d631c9336b861523592ff217fe823436b36
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/nvidia/ck804/acpi/ck804.asl
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/smbus.h
4 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/25879/1

diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl
index aac7ea8..4a83b84 100644
--- a/src/southbridge/nvidia/ck804/acpi/ck804.asl
+++ b/src/southbridge/nvidia/ck804/acpi/ck804.asl
@@ -54,7 +54,7 @@

/* set "B", external (PCI) APIC interrupts */
 Name (PRSB, ResourceTemplate () {
-	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {
+	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) {
    	16, 17, 18, 19,
    }
 })
@@ -93,7 +93,7 @@

/* set "C", southbridge APIC interrupts */
 Name (PRSC, ResourceTemplate () {
-	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {
+	Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) {
    	20, 21, 22, 23,
    }
 })
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 8019a8e..6ddd59e 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -83,7 +83,7 @@
    };

int j;
-	for (j = 0; j < mcp55_num; j++ ) {
+	for (j = 0; j < mcp55_num; j++) {
    	setup_resource_map_offset(ctrl_devport_conf,
    		ARRAY_SIZE(ctrl_devport_conf),
    		PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
@@ -100,7 +100,7 @@
    };

int j;
-	for (j = 0; j < mcp55_num; j++ ) {
+	for (j = 0; j < mcp55_num; j++) {
    	setup_resource_map_offset(ctrl_devport_conf_clear,
    		ARRAY_SIZE(ctrl_devport_conf_clear),
    		PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index eeb6c1b..180b9a8 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -131,7 +131,7 @@
    if (nmi_option)
    	byte &= ~(1 << 7); /* Set NMI. */
    else
-		byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
+		byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
    if (byte != byte_old)
    	outb(byte, 0x70);

diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index a588a09..274ccfe 100644
--- a/src/southbridge/nvidia/mcp55/smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
@@ -45,7 +45,7 @@
    	smbus_delay();

val = inb(smbus_io_base + SMBHSTSTAT);
-		if ( (val & 0xff) != 0) {
+		if ((val & 0xff) != 0) {
    		return 0;
    	}
    } while (--loops);