Attention is currently required from: Furquan Shaikh, Paul Menzel, Sumeet R Pawnikar, Rajasekhar Venkatanagapavan, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Rajasekhar Venkatanagapavan, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/54676
to look at the new patch set (#8).
Change subject: soc/intel/adl: Add SKU specific power limits support ......................................................................
soc/intel/adl: Add SKU specific power limits support
Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501.
BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/systemagent.c 5 files changed, 61 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/54676/8