Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856
-gerrit
commit 384a4f2840ff3d725caed752a7f2f3d505a36165 Author: Arthur Heymans arthur@aheymans.xyz Date: Mon Oct 3 17:16:48 2016 +0200
nb/intel/i945: make pci_mmio_size a cmos option
Instead of hardcoding pci_mmio_size in raminit code, make this a cmos option.
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/mainboard/apple/macbook21/cmos.default | 3 ++- src/mainboard/apple/macbook21/cmos.layout | 15 ++++++++++++--- src/mainboard/lenovo/t60/cmos.default | 3 ++- src/mainboard/lenovo/t60/cmos.layout | 15 ++++++++++++--- src/mainboard/lenovo/x60/cmos.default | 3 ++- src/mainboard/lenovo/x60/cmos.layout | 15 ++++++++++++--- src/northbridge/intel/i945/raminit.c | 9 ++++++--- 7 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 1cf350c..da61c1f 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -17,4 +17,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 8329347..83f5111 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -60,9 +60,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail
-# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -70,6 +67,10 @@ entries 937 1 e 1 lpt #938 46 r 0 unused
+# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -126,6 +127,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index 03b92e3..ea97a84 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -18,4 +18,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 2cd4e7b..37d7aba 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -58,9 +58,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail
-# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -72,6 +69,10 @@ entries 944 1 e 2 hyper_threading #945 7 r 0 unused
+# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -129,6 +130,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 4e72734..4f71a45 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -18,4 +18,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 3e316c9..1936271 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -58,9 +58,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail
-# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -72,6 +69,10 @@ entries 944 1 e 2 hyper_threading #945 7 r 0 unused
+# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -129,6 +130,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..dfe8fd1 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -26,6 +26,7 @@ #include "raminit.h" #include "i945.h" #include <cbmem.h> +#include <pc80/mc146818rtc.h>
/* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -1503,7 +1504,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size;
printk(BIOS_DEBUG, "Setting RAM size...\n");
@@ -1541,9 +1542,11 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) /* The TOM register has a different format */ tom = tolud >> 3;
+ pci_mmio_size = 0x2; /* use 768M as default */ + get_option(&pci_mmio_size, "pci_mmio_size"); + /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + tolud = MIN(0x100 - ((pci_mmio_size + 1) << 4), tolud);
pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);