[coreboot-gerrit] [XS] Change in coreboot[main]: ec/google/chromeec: Fill typec ssdt based on TCSS mux config

[Krishna P Bhat D (Code Review)]

Attention is currently required from: Caveh Jalali, Forest Mittelberg.

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82134?usp=email )

Change subject: ec/google/chromeec: Fill typec ssdt based on TCSS mux config
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ec/google/chromeec: Fill typec ssdt based on TCSS mux config

In platforms that use PDC<->PMC direct connection to perform mux
configuration, PDC directly communicates the type-c port info to PMC.
Therefore, kernel does not need to talk to EC and PMC for mux
configuration.

cros_ec_typec driver in kernel provides support for accessing the Type-C
information from Chrome OS EC. Now with TCSS using PDC<->OMC mux config,
this driver is not required to be loaded in kernel to get typec port
connector information. So do not create a USB Type-C control ACPI
device.

BUG=b:332383540
TEST=Build and boot to OS on brox. Check SSDT before and after this
patch for USB Type-C device ID.

Change-Id: I0ffe8a1b444be9d330d71e9c967b5afa85b262b3
Signed-off-by: Krishna Prasad Bhat 
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/82134/1

diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 61d1e5c..67e5325 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -285,7 +285,9 @@
    if (CONFIG(DRIVERS_INTEL_DPTF))
    	ec_fill_dptf_helpers(ec, dev);

-	fill_ssdt_typec_device(dev);
+	if (!CONFIG(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION))
+		fill_ssdt_typec_device(dev);
+
    fill_ssdt_ps2_keyboard(dev);
 }