Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056
-gerrit
commit b78f7eeef9cf6149058194771a43cfcfc31c7c5f Author: Hannah Williams hannah.williams@intel.com Date: Thu Jun 2 15:00:36 2016 -0700
board/intel/amenia: Enable LPSS PMCTL for S0ix
This setting will enable S0ix for LPSS
Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/mainboard/intel/amenia/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 38a2de2..77ae0bf 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD
+ # LPSS IOSF PMCTL S0ix Enable + register "S0ixEnable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF