[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Intel Xeon Scalable Processor support

[Anjaneya "Reddy" Chagam (Code Review)]

Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )

Change subject: soc/intel: Add Intel Xeon Scalable Processor support
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Patch Set 44:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
PS41, Line 33: 		.CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
             : 		.CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
> So this change is causing a regression? Why land something that is broken? There's also only so much […]

I am going to push this change and move on!! Issue happens sporadically on 2S Tioga Pass Server where PCU mail box command times out. This will take time to debug considering this is happening very late in the boot flow (post silicon init).