Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58132 )
Change subject: soc/intel/alderlake: Add the CnviDdrRfim configuration ......................................................................
soc/intel/alderlake: Add the CnviDdrRfim configuration
FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfim to 1 enable CNVi DDR RFIM
BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index afabcf0..771fc5a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -554,6 +554,11 @@ * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ uint8_t SlowSlewRate[NUM_VR_DOMAINS]; + + /* CNVi DDR RFIM Enable/Disable + * Default 0. Setting this to 1 enable CNVi DDR RFIM. + */ + bool CnviDdrRfim; };
typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 121251e..2d63141 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -207,6 +207,9 @@
/* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */ m_cfg->SkipMbpHob = 1; + + /* CNVi DDR RFI Mitigation */ + m_cfg->CnviDdrRfim = config->CnviDdrRfim; }
static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,