[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Make TSEG_BASE align to TSEG_SIZE

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36542 )

Change subject: soc/intel/icelake: Make TSEG_BASE align to TSEG_SIZE
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soc/intel/icelake: Make TSEG_BASE align to TSEG_SIZE

Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik 
---
M src/soc/intel/icelake/smmrelocate.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36542/1

diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index edcc49d..6ac17a2 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -178,6 +178,7 @@
    const u32 rmask = ~(4 * KiB - 1);

smm_region(&tseg_base, &tseg_size);
+	tseg_base = ALIGN(tseg_base, tseg_size);
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */