Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74844 )
Change subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte ......................................................................
soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
The memory map granularity for those devices is 4kByte.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 17 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923..5b836ea 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -121,7 +121,7 @@ FLASH_BELOW_4GB_MAPPING_REGION_SIZE);
/* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);
res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR;