[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/fast_spi: Add extended decode window support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )

Change subject: soc/intel/common/fast_spi: Add extended decode window support
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... 
File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... 
PS4, Line 327: fast_spi_enable_ext_bios
This will have to be done outside of MMIO space enabling. Reason is because fast_spi_enable_ext_bios() calls fast_spi_get_ext_bios_window() to get base and size of BIOS region. For that, MMIO space needs to be enabled. So, the flow will have to be:

void fast_spi_early_init(uintptr_t spi_base_address)
{
        ...
     	/* Program Temporary BAR for SPI */
    pci_write_config32(dev, PCI_BASE_ADDRESS_0,
    	spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);

/* Enable Bus Master and MMIO Space */
    pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

/* Initialize SPI to allow BIOS to write/erase on flash. */
    fast_spi_init();

/* Enable extended bios support */
    fast_spi_enable_ext_bios();
}

and

static void fast_spi_enable_ext_bios(void)
{
    ...

fast_spi_get_ext_bios_window(&ext_bios_base, &ext_bios_size);
    ...

pcireg = pci_read_config16(dev, PCI_COMMAND);
    pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
    pci_write_config16(dev, PCI_COMMAND, pcireg);

/* Perform GPMR, BAR1 and other configuration */
    ...

pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

}