[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Add support to read and set SPI speeds from verstage

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58115 )

Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage
......................................................................

Patch Set 1:

(1 comment)

File src/soc/amd/common/block/psp/psp_efs.c:

https://review.coreboot.org/c/coreboot/+/58115/comment/361a31a6_99effe81 
PS1, Line 14: efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
> This hard-coded EFS address works in x86. […]

Oh that's not confusing. This file is under /psp and called psp_efs. I thought it was only called from PSP verstage. Can you delete the EFS_ADDRESS #define since we shouldn't need it anymore.