[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42885 )

Change subject: soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned
......................................................................

soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned

The bootblock must be 16-bit aligned for it to boot.

BUG=b:159081993
TEST=Made sure trembyle still compiles.

Signed-off-by: Raul E Rangel 
Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
---
M src/soc/amd/picasso/memlayout.ld
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld
index a82e303..6f43ba1 100644
--- a/src/soc/amd/picasso/memlayout.ld
+++ b/src/soc/amd/picasso/memlayout.ld
@@ -81,6 +81,7 @@
    FMAP_CACHE(., FMAP_SIZE)

_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
+	_ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned");
    BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
    ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
    REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)