Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46352 )
Change subject: soc/intel/broadwell: Drop reg-script usage from bootblock PCH init ......................................................................
Patch Set 8: Code-Review+2
(6 comments)
https://review.coreboot.org/c/coreboot/+/46352/2/src/soc/intel/broadwell/boo... File src/soc/intel/broadwell/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/46352/2/src/soc/intel/broadwell/boo... PS2, Line 63: pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010);
Oops, slipped through. […]
Done
https://review.coreboot.org/c/coreboot/+/46352/2/src/soc/intel/broadwell/boo... PS2, Line 79:
Was there on Lynxpoint, will drop
Done
https://review.coreboot.org/c/coreboot/+/46352/2/src/soc/intel/broadwell/boo... PS2, Line 84: It's affected by posted write syndrome.
That's neither helpful for people who understand posting writes nor for […]
Done
https://review.coreboot.org/c/coreboot/+/46352/2/src/soc/intel/broadwell/boo... PS2, Line 85: RCBA32(HPTC);
Why use a (void) cast above to make it clear that the value is discarded […]
Done
https://review.coreboot.org/c/coreboot/+/46352/8/src/soc/intel/broadwell/boo... File src/soc/intel/broadwell/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/46352/8/src/soc/intel/broadwell/boo... PS8, Line 70: /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ GAMEL not mentioned?
https://review.coreboot.org/c/coreboot/+/46352/8/src/soc/intel/broadwell/boo... PS8, Line 91: (void *)HPET_BASE_ADDRESS + 0x10 Technically this is undefined (but we know what GCC will do). The cast takes precedence and then you do pointer arithmetic on a void pointer.