[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Enable end of post support in FSP

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40612 )

Change subject: soc/intel/jasperlake: Enable end of post support in FSP
......................................................................

soc/intel/jasperlake: Enable end of post support in FSP

Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

Change-Id: Ie21dcfc84d331f036090d01ea3e3925b81eea902
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40612
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
---
M src/soc/intel/jasperlake/fsp_params.c
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 28dccab..38138be 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -14,6 +14,18 @@
 #include <soc/soc_chip.h>
 #include <string.h>

+/*
+ * ME End of Post configuration
+ * 0 - Disable EOP.
+ * 1 - Send in PEI (Applicable for FSP in API mode)
+ * 2 - Send in DXE (Not applicable for FSP in API mode)
+ */
+enum {
+	EOP_DISABLE,
+	EOP_PEI,
+	EOP_DXE,
+} EndOfPost;
+
 static const pci_devfn_t serial_io_dev[] = {
    PCH_DEVFN_I2C0,
    PCH_DEVFN_I2C1,
@@ -97,6 +109,9 @@
    /* Unlock upper 8 bytes of RTC RAM */
    params->RtcMemoryLock = 0;

+	/* Enable End of Post in PEI phase */
+	params->EndOfPostMessage = EOP_PEI;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = 1;