Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32237 )
Change subject: WIP: Add complete board list with no-blob/blob status ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32237/3/Documentation/mainboard-blob-status.... File Documentation/mainboard-blob-status.csv:
https://review.coreboot.org/#/c/32237/3/Documentation/mainboard-blob-status.... PS3, Line 21: sifive/hifive-unleashed,?,Sifive soc
Y afaik (ram training runs somewhere else, iirc)
Short answer: Y
Longer answer: RAM init happens in coreboot. The boot ROM hasn't been fully reproduced from C code (see https://github.com/sifive/freedom-u540-c000-bootloader/pull/7), but source is available. and the boot ROM can be bypassed (see https://doc.coreboot.org/mainboard/sifive/hifive-unleashed.html#boot-modes), although I'm not sure if the current version of coreboot can run properly when the boot ROM didn't run first (the boot ROM handles CAR init if it runs).