[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Generate SPCR table

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 )

Change subject: soc/amd/stoneyridge: Generate SPCR table
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/25345/6/src/soc/amd/stoneyridge/uar... 
File src/soc/amd/stoneyridge/uart.c:

https://review.coreboot.org/c/coreboot/+/25345/6/src/soc/amd/stoneyridge/uar... 
PS6, Line 41: AMDCZ
> Works for me, not that I will get to this any time soon... […]

I think we can remove all the special AMDCZ handling. The AMD part uses DW IP. The driver supports reading the fixed clock rate: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...

So if we pass that along then I think the kernel will configure the IP correctly so we can boot with console=ttyS0 even when coreboot hasn't setup the UART.

I need to try this out on zork.