Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: AMD AGESA, binaryPI: implement C bootblock ......................................................................
AMD AGESA, binaryPI: implement C bootblock
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/amd/pi/Kconfig M src/cpu/amd/pi/romstage.c M src/cpu/x86/lapic/Makefile.inc M src/drivers/amd/agesa/Makefile.inc A src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/cache_as_ram.S A src/drivers/amd/agesa/exit_car.S M src/drivers/amd/agesa/romstage.c M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 13 files changed, 157 insertions(+), 138 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36914/1
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d14eb40..65f2b44 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -30,6 +30,8 @@ select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK +
if CPU_AMD_AGESA
@@ -49,6 +51,11 @@ hex default 0x10000
+config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config ENABLE_MRC_CACHE bool "Use cached memory configuration" default n diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index c4a92cf..aa0c05c 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -11,6 +11,8 @@ # GNU General Public License for more details. #
+bootblock-y += fixme.c + romstage-y += fixme.c
ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index b33302e..82dc9e8 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -29,6 +29,7 @@ select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK
if CPU_AMD_PI
@@ -51,6 +52,11 @@ hex default 0x10000
+config DCACHE_BSP_STACK_SIZE + hex + depends on C_ENVIRONMENT_BOOTBLOCK + default 0x4000 + config S3_DATA_POS hex default 0xFFFF0000 diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index cac5664..f060dc2 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -21,11 +21,6 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h>
-void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void *asmlinkage romstage_main(unsigned long bist) { int s3resume = 0; diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..0d11478 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index 4d5bd3e..be048c4 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -21,8 +21,8 @@
ramstage-y += state_machine.c
-cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S -postcar-y += cache_as_ram.S +bootblock-y += cache_as_ram.S +postcar-y += exit_car.S
else
@@ -30,6 +30,8 @@
endif
+bootblock-y += bootblock.c + romstage-y += def_callouts.c romstage-y += eventlog.c
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c new file mode 100644 index 0000000..1a6bfdb --- /dev/null +++ b/src/drivers/amd/agesa/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + amd_initmmio(); + enable_lapic(); + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_basetime(timestamp_get()); +} \ No newline at end of file diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index dcb0c43..707615d 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -25,14 +25,14 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
-.code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end -.globl chipset_teardown_car +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */
-_cache_as_ram_setup: - - /* Preserve BIST. */ - movd %eax, %mm0 +.global bootblock_pre_c_entry +bootblock_pre_c_entry:
post_code(0xa0)
@@ -43,128 +43,35 @@ orl $(3 << 9), %eax movl %eax, %cr4
- post_code(0xa1)
AMD_ENABLE_STACK
- /* Align the stack. */ - and $0xFFFFFFF0, %esp - -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx + /* Setup bootblock stack on BSP */ + mov $0x1b, %ecx rdmsr - bts $8, %eax - wrmsr + test $256, %eax + jz stack_align
- # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 + mov $_ecar_stack, %esp
- # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: +stack_align:
-#endif + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $8, %esp
- call early_all_cores + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */
- /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main +before_carstage: + post_code(0xa2)
-#if CONFIG(POSTCAR_STAGE) + call bootblock_c_entry + /* Never reached */
-/* We do not return. Execution continues with run_postcar_phase() - * calling to chipset_teardown_car below. - */ - jmp postcar_entry_failure - -chipset_teardown_car: - -/* - * Retrieve return address from stack as it will get trashed below if - * execution is utilizing the cache-as-ram stack. - */ - pop %esp - -#else - - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. */ - -#endif - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -/* Register %esp is preserved in AMD_DISABLE_STACK. */ - AMD_DISABLE_STACK - -#if CONFIG(POSTCAR_STAGE) - - jmp *%esp - -#else - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - -#endif - - /* Should never see this postcode */ - post_code(0xaf) - -stop: +.halt_forever: + post_code(POST_DEAD_CODE) hlt - jmp stop - -/* These are here for linking purposes. */ -.weak early_all_cores, romstage_main -early_all_cores: -romstage_main: -postcar_entry_failure: - /* Should never see this postcode */ - post_code(0xae) - jmp stop - -_cache_as_ram_setup_end: + jmp .halt_forever diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S new file mode 100644 index 0000000..f9d056e --- /dev/null +++ b/src/drivers/amd/agesa/exit_car.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gcccar.inc> +#include <cpu/x86/cache.h> + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + pop %esp + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $(~(CR0_CD | CR0_NW)), %eax + movl %eax, %cr0 + + jmp *%esp diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 76a6ea4..bfdbda3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -34,11 +34,6 @@ #error "LEGACY_WRAPPER code not supported" #endif
-void asmlinkage early_all_cores(void) -{ - amd_initmmio(); -} - void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -52,7 +47,7 @@ agesa_set_interface(cb); }
-void *asmlinkage romstage_main(unsigned long bist) +void asmlinkage car_stage_entry(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -75,9 +70,6 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1));
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET);
agesa_execute_state(cb, AMD_INIT_EARLY); @@ -109,6 +101,5 @@ recover_postcar_frame(&pcf, cb->s3resume);
run_postcar_phase(&pcf); - /* We do not return. */ - return NULL; + /* We do not return. */ } diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4b4b138..6199b24 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,6 +28,8 @@ # #*****************************************************************************
+bootblock-y += bootblock.c +bootblock-y += early_setup.c bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..3899783 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -13,8 +13,12 @@ * GNU General Public License for more details. */
+#include <bootblock_common.h> #include <stdint.h> +#include <arch/io.h> #include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <southbridge/amd/pi/hudson/hudson.h>
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -60,3 +64,40 @@ { hudson_enable_rom(); } + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..08adb84 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0)
+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPI_CNTRL0 0x00