Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35172 )
Change subject: soc/intel/skylake: Clean up ......................................................................
Patch Set 7: Code-Review+2
(49 comments)
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... File src/soc/intel/skylake/acpi.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 265: fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | hm, this will break from time to time when things get added and removed... what about putting each in a separate line?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 523: } newline?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/acpi.... PS7, Line 683: pm1_en |= PWRBTN_STS; newline
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 33: -- why not a single dash?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/bootb... PS7, Line 110: uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 separate lines?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 7: #include <arch/acpi_device.h> : #include <device/i2c_simple.h> : #include <drivers/i2c/designware/dw_i2c.h> : #include <intelblocks/cfg.h> : #include <intelblocks/gspi.h> : #include <intelblocks/lpc_lib.h> : #include <stdint.h> : #include <soc/gpe.h> : #include <soc/gpio.h> : #include <soc/irq.h> : #include <soc/pci_devs.h> : #include <soc/pmc.h> : #include <soc/serialio.h> : #include <soc/usb.h> : #include <soc/vr_config.h> : #include <smbios.h> order
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 146: System Agent Geyserville maybe add a hint that this is SpeedStep?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 245: * 0: Disable Root Port : * 1: Enable Root Port : simply drop "Root Port"?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 252: * 0: Disable Clk-Req : * 1: Enable Clk-req : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 269: * 0: Disable AER : * 1: Enable AER : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 276: * 0: Disable LTR : * 1: Enable LTR : same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 361: /* GPIO IRQ Route The valid values is 14 or 15*/ /* GPIO IRQ Route: valid values are 14 or 15 */
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 363: /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ /* SCI IRQ Select: valid values are 9, 10, 11, 20, 21, 22, 23 */
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 443: * Values 0: Disabled, 1: Enabled keep convention: each on a new line
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 447: /* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled */ same
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 480: one space too much; each on a new line maybe?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 485: * HeciEnabled decides the state of HECI1 at end of boot : * Setting to 0 (default) disables HECI1 and hides the device from OS : missing dots
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 4: clude <bootmode.h> : #include <bootstate.h> : #include <cbmem.h> : #include <fsp/api.h> : #include <arch/acpi.h> : #include <console/console.h> : #include <device/device.h> : #include <device/pci_ids.h> : #include <fsp/util.h> order
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 192: r( space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 193: id( space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 265: tconfig->SataTestMode = config->SataTestMode; maybe move to line 258 to group sata stuff together?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/chip.... PS7, Line 266: /* newline before
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/cpu.c... PS7, Line 388: msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | : (ACPI_BASE_ADDRESS + PM1_TMR); : each on new line?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... File src/soc/intel/skylake/finalize.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/final... PS7, Line 91: * we uc
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... File src/soc/intel/skylake/gpio.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/gpio.... PS7, Line 54: : static const struct pad_community skl_gpio_communities[] = { : { : .port = PID_GPIOCOM0, : .first_pad = GPP_A0, : .last_pad = GPP_B23, : .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM0", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com0_groups, : .num_groups = ARRAY_SIZE(skl_community_com0_groups), : }, { : .port = PID_GPIOCOM1, : .first_pad = GPP_C0, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .last_pad = GPP_H23, : #else : .last_pad = GPP_E23, : #endif : .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM1", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com1_groups, : .num_groups = ARRAY_SIZE(skl_community_com1_groups), : }, { : .port = PID_GPIOCOM3, : #if CONFIG(SKYLAKE_SOC_PCH_H) : .first_pad = GPP_I0, : .last_pad = GPP_I10, : #else : .first_pad = GPP_F0, : .last_pad = GPP_G7, : #endif : .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM3", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map, : .num_reset_vals = ARRAY_SIZE(rst_map), : .groups = skl_community_com3_groups, : .num_groups = ARRAY_SIZE(skl_community_com3_groups), : }, { : .port = PID_GPIOCOM2, : .first_pad = GPD0, : .last_pad = GPD11, : .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, : .pad_cfg_base = PAD_CFG_BASE, : .host_own_reg_0 = HOSTSW_OWN_REG_0, : .gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, : .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, : .gpi_smi_en_reg_0 = GPI_SMI_EN_0, : .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, : .name = "GPIO_COM2", : .acpi_path = "\_SB.PCI0.GPIO", : .reset_map = rst_map_com2, : .num_reset_vals = ARRAY_SIZE(rst_map_com2), : .groups = skl_community_com2_groups, : .num_groups = ARRAY_SIZE(skl_community_com2_groups), : } : }; <3
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 30: one tab is enough
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/device_nvs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: #define SIO_NVS_I2C0 0 : #define SIO_NVS_I2C1 1 : #define SIO_NVS_I2C2 2 : #define SIO_NVS_I2C3 3 : #define SIO_NVS_I2C4 4 : #define SIO_NVS_I2C5 5 : #define SIO_NVS_SPI0 6 : #define SIO_NVS_SPI1 7 : #define SIO_NVS_UART0 8 : #define SIO_NVS_UART1 9 : #define SIO_NVS_UART2 10 : one tab
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: #define GPE0_DW0_00 0 : #define GPE0_DW0_01 1 : #define GPE0_DW0_02 2 : #define GPE0_DW0_03 3 : #define GPE0_DW0_04 4 : #define GPE0_DW0_05 5 : #define GPE0_DW0_06 6 : #define GPE0_DW0_07 7 : #define GPE0_DW0_08 8 : #define GPE0_DW0_09 9 : #define GPE0_DW0_10 10 : #define GPE0_DW0_11 11 : #define GPE0_DW0_12 12 : #define GPE0_DW0_13 13 : #define GPE0_DW0_14 14 : #define GPE0_DW0_15 15 : #define GPE0_DW0_16 16 : #define GPE0_DW0_17 17 : #define GPE0_DW0_18 18 : #define GPE0_DW0_19 19 : #define GPE0_DW0_20 20 : #define GPE0_DW0_21 21 : #define GPE0_DW0_22 22 : #define GPE0_DW0_23 23 : #define GPE0_DW0_24 24 : #define GPE0_DW0_25 25 : #define GPE0_DW0_26 26 : #define GPE0_DW0_27 27 : #define GPE0_DW0_28 28 : #define GPE0_DW0_29 29 : #define GPE0_DW0_30 30 : #define GPE0_DW0_31 31 : /* GPE_63_32 */ : #define GPE0_DW1_00 32 : #define GPE0_DW1_01 33 : #define GPE0_DW1_02 34 : #define GPE0_DW1_03 36 : #define GPE0_DW1_04 36 : #define GPE0_DW1_05 37 : #define GPE0_DW1_06 38 : #define GPE0_DW1_07 39 : #define GPE0_DW1_08 40 : #define GPE0_DW1_09 41 : #define GPE0_DW1_10 42 : #define GPE0_DW1_11 43 : #define GPE0_DW1_12 44 : #define GPE0_DW1_13 45 : #define GPE0_DW1_14 46 : #define GPE0_DW1_15 47 : #define GPE0_DW1_16 48 : #define GPE0_DW1_17 49 : #define GPE0_DW1_18 50 : #define GPE0_DW1_19 51 : #define GPE0_DW1_20 52 : #define GPE0_DW1_21 53 : #define GPE0_DW1_22 54 : #define GPE0_DW1_23 55 : #define GPE0_DW1_24 56 : #define GPE0_DW1_25 57 : #define GPE0_DW1_26 58 : #define GPE0_DW1_27 59 : #define GPE0_DW1_28 60 : #define GPE0_DW1_29 61 : #define GPE0_DW1_30 62 : #define GPE0_DW1_31 63 : /* GPE_95_64 */ : #define GPE0_DW2_00 64 : #define GPE0_DW2_01 65 : #define GPE0_DW2_02 66 : #define GPE0_DW2_03 67 : #define GPE0_DW2_04 68 : #define GPE0_DW2_05 69 : #define GPE0_DW2_06 70 : #define GPE0_DW2_07 71 : #define GPE0_DW2_08 72 : #define GPE0_DW2_09 73 : #define GPE0_DW2_10 74 : #define GPE0_DW2_11 75 : #define GPE0_DW2_12 76 : #define GPE0_DW2_13 77 : #define GPE0_DW2_14 78 : #define GPE0_DW2_15 79 : #define GPE0_DW2_16 80 : #define GPE0_DW2_17 81 : #define GPE0_DW2_18 82 : #define GPE0_DW2_19 83 : #define GPE0_DW2_20 84 : #define GPE0_DW2_21 85 : #define GPE0_DW2_22 86 : #define GPE0_DW2_23 87 : #define GPE0_DW2_24 88 : #define GPE0_DW2_25 89 : #define GPE0_DW2_26 90 : #define GPE0_DW2_27 91 : #define GPE0_DW2_28 92 : #define GPE0_DW2_29 93 : #define GPE0_DW2_30 94 : #define GPE0_DW2_31 95 : /* GPE_STD */ : #define GPE0_HOT_PLUG 97 : #define GPE0_SWGPE 98 : #define GPE0_TCOSCI 102 : #define GPE0_SMB_WAK 103 : #define GPE0_PCI_EXP 105 : #define GPE0_BATLOW 106 : #define GPE0_PME 107 : #define GPE0_ME_SCI 108 : #define GPE0_PME_B0 109 : #define GPE0_ESPI 110 : #define GPE0_GPIO_T2 111 : #define GPE0_LAN_WAK 112 : #define GPE0_WADT 114 : : #define GPE_MAX GPE0_WADT : one tab?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 210: GPIO_MISCCFG 0x10 : #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 : #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 : #define HOSTSW_OWN_REG_0 0xd0 : #define PAD_CFG_BASE 0x400 : #define GPI_INT_STS_0 0x100 : #define GPI_INT_EN_0 0x120 : #define GPI_SMI_STS_0 0x180 : #define GPI_SMI_EN_0 0x1a0 aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 12: e PCH_PRESERVED_BASE_ADDRESS 0xfc800000 : #define PCH_PRESERVED_BASE_SIZE 0x02000000 alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/irq.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 6: : #define GPIO_IRQ14 14 : #define GPIO_IRQ15 15 : : #define PCH_IRQ10 10 : #define PCH_IRQ11 11 : : #define SCI_IRQ9 9 : #define SCI_IRQ10 10 : #define SCI_IRQ11 11 : #define SCI_IRQ20 20 : #define SCI_IRQ21 21 : #define SCI_IRQ22 22 : #define SCI_IRQ23 23 : : #define TCO_IRQ9 9 : #define TCO_IRQ10 10 : #define TCO_IRQ11 11 : #define TCO_IRQ20 20 : #define TCO_IRQ21 21 : #define TCO_IRQ22 22 : #define TCO_IRQ23 23 : : #define LPSS_I2C0_IRQ 16 : #define LPSS_I2C1_IRQ 17 : #define LPSS_I2C2_IRQ 18 : #define LPSS_I2C3_IRQ 19 : #define LPSS_I2C4_IRQ 34 : #define LPSS_I2C5_IRQ 33 : #define LPSS_SPI0_IRQ 22 : #define LPSS_SPI1_IRQ 23 : #define LPSS_UART0_IRQ 20 : #define LPSS_UART1_IRQ 21 : #define LPSS_UART2_IRQ 32 : #define SDIO_IRQ 22 : : #define cAVS_INTA_IRQ 16 : #define SMBUS_INTA_IRQ 16 : #define SMBUS_INTB_IRQ 17 : #define GbE_INTA_IRQ 16 : #define GbE_INTC_IRQ 18 : #define TRACE_HUB_INTA_IRQ 16 : #define TRACE_HUB_INTD_IRQ 19 : : #define eMMC_IRQ 21 : #define SD_IRQ 23 : : #define PCIE_1_IRQ 16 : #define PCIE_2_IRQ 17 : #define PCIE_3_IRQ 18 : #define PCIE_4_IRQ 19 : #define PCIE_5_IRQ 16 : #define PCIE_6_IRQ 17 : #define PCIE_7_IRQ 18 : #define PCIE_8_IRQ 19 : #define PCIE_9_IRQ 16 : #define PCIE_10_IRQ 17 : #define PCIE_11_IRQ 18 : #define PCIE_12_IRQ 19 : : #define SATA_IRQ 16 : : #define HECI_1_IRQ 16 : #define HECI_2_IRQ 17 : #define IDER_IRQ 18 : #define KT_IRQ 19 : #define HECI_3_IRQ 16 : : #define XHCI_IRQ 16 : #define OTG_IRQ 17 : #define THERMAL_IRQ 18 : #define CIO_INTA_IRQ 16 : #define CIO_INTD_IRQ 19 : #define ISH_IRQ 20 : : #define PEG_RP_INTA_IRQ 16 : #define PEG_RP_INTB_IRQ 17 : #define PEG_RP_INTC_IRQ 18 : #define PEG_RP_INTD_IRQ 19 : : #define IGFX_IRQ 16 : #define SA_THERMAL_IRQ 16 : #define SKYCAM_IRQ 16 : #define GMM_IRQ 16 aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/me.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 37: #define ME_HFS2_PHASE_ROM 0 : #define ME_HFS2_PHASE_UKERNEL 2 : #define ME_HFS2_PHASE_BUP 3 : #define ME_HFS2_PHASE_HOST_COMM 6 : /* Current State - Based on Infra Progress values. */ : /* ROM State */ : #define ME_HFS2_STATE_ROM_BEGIN 0 : #define ME_HFS2_STATE_ROM_DISABLE 6 : /* BUP State */ : #define ME_HFS2_STATE_BUP_INIT 0 : #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 : #define ME_HFS2_STATE_BUP_CG_ENABLE 2 : #define ME_HFS2_STATE_BUP_PM_HND_EN 3 : #define ME_HFS2_STATE_BUP_FLOW_DET 4 : #define ME_HFS2_STATE_BUP_PMC_PATCHING 5 : #define ME_HFS2_STATE_BUP_GET_FLASH_VSCC 6 : #define ME_HFS2_STATE_BUP_SET_FLASH_VSCC 7 : #define ME_HFS2_STATE_BUP_VSCC_ERR 8 : #define ME_HFS2_STATE_BUP_EFSS_INIT 9 : #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa : #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb : #define ME_HFS2_STATE_BUP_STRAP_DIS 0xc : #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd : #define ME_HFS2_STATE_BUP_M3 0x11 : #define ME_HFS2_STATE_BUP_M0 0x12 : #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 : #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 : #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 : #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 : #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c : #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f : #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 : #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 : #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 : #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 : #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 : #define ME_HFS2_STATE_BUP_M0_CLK 0x26 : #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 : #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 : #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 : /* Policy Module State */ : #define ME_HFS2_STATE_POLICY_ENTRY 0 : #define ME_HFS2_STATE_POLICY_RCVD_S3 3 : #define ME_HFS2_STATE_POLICY_RCVD_S4 4 : #define ME_HFS2_STATE_POLICY_RCVD_S5 5 : #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 : #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 : #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 : #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 : #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa : #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb : #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc : #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd : #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe : #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf : #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 : /* Current PM Event Values */ : #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 : #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 : #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 : #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 : #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 : #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 : #define ME_HFS2_PMEVENT_CM0_CM3 7 : #define ME_HFS2_PMEVENT_CM3_CM0 8 : #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa : #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb : #define ME_HFS2_PMEVENT_CMX_CMOFF 0xc : #define ME_HFS2_PMEVENT_CM0_CM0PG 0xd : #define ME_HFS2_PMEVENT_CM3_CM3PG 0xe : #define ME_HFS2_PMEVENT_CM0PG_CM0 0xf ugh. aligment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/nhlt.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 9: ID 0x8086 : #define NHLT_DID_DMIC 0xae20 : #define NHLT_DID_BT 0xae30 : #define NHLT_DID_SSP 0xae alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 10: 0x6c : #define PCH_P2SB_HBDF 0x70 : : #define PCH_P2SB_EPMASK0 0xB0 : : #define PCH_PWRM_ACPI_TMR_CTL 0xFC aligmnet
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 40: OCK (1 << 18) : #define ACPI_BASE_LOCK (1 << 17) : #define SUS_PWR_FLR (1 << 14) : #define WOL_EN_OVRD (1 << 13) : #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) : #define SLP_S3_MIN_ASST_WDTH_MASK (0x3 << 10) : #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) : #define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10) : #define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10) : #define SLP_S3_MIN_ASST_WDTH_2S (3 << 10) : #define HOST_RST_STS (1 << 9) o.O
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/smbus.h:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/inclu... PS7, Line 8: 0x04 : #define TCO_TIMEOUT (1 << 3) : #define TCO2_STS 0x06 : #define TCO_STS_SECOND_TO (1 << 1) : #define TCO_INTRD_DET (1 << 0) : #define TCO1_CNT 0x08 : #define TCO_LOCK (1 << 12) : #define TCO_TMR_HLT (1 << 11) : #define TCO2_CNT 0x0A : #define TCO_INTRD_SEL_MASK (3 << 1) : #define TCO_INTRD_SEL_SMI (1 << 2) : #define TCO_INTRD_SEL_INT (1 << 1) one tab less is enough
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/da7219.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 54: huh?
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/dmic.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 97: ARRAY_SIZE(dmic_2ch_descriptors)); : case 4: : return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, : ARRAY_SIZE(dmi instead of removing one tab, adding 2 spaces would be right I think
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98357.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 34: misaligned
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98373.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 83: nts(nhlt, hwlink, max98373_descriptors, : AR alignment was correct here
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 73: ARRAY this looks wrong
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/max98927.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 35: drop one space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 36: ile = "max9 alignment
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 64: ARR no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/nau88l25.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: ARRA no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5514.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 14: drop one space
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 45: AR no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/rt5663.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 59: A no
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... File src/soc/intel/skylake/nhlt/ssm4567.c:
https://review.coreboot.org/c/coreboot/+/35172/7/src/soc/intel/skylake/nhlt/... PS7, Line 57: A no