coreboot-gerrit April 2025

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[S] Change in coreboot[main]: ec/system76/ec: Add config for 2nd fan without GPU
by Tim Crawford (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Jeremy Soller. Hello Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87068?usp=email to look at the new patch set (#2). Change subject: ec/system76/ec: Add config for 2nd fan without GPU ...................................................................... ec/system76/ec: Add config for 2nd fan without GPU The darp10 has a second fan but no dGPU. The NFAN Method must exist, so use the default hwmon names of "fan1" and "fan2" for labels. Change-Id: I553deefea374b9dd916be6611850fca61afd490d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/ec/system76/ec/Kconfig M src/ec/system76/ec/acpi/s76.asl M src/mainboard/system76/mtl/Kconfig 3 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/87068/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I553deefea374b9dd916be6611850fca61afd490d Gerrit-Change-Number: 87068 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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[S] Change in coreboot[main]: ec/system76/ec: Add config for 2nd fan without GPU
by Tim Crawford (Code Review) 01 Apr '25

01 Apr '25

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87068?usp=email ) Change subject: ec/system76/ec: Add config for 2nd fan without GPU ...................................................................... ec/system76/ec: Add config for 2nd fan without GPU The darp10 has a second fan but no dGPU. The NFAN Method must exist, so use the default hwmon names of "fan1" and "fan2" for labels. Change-Id: I553deefea374b9dd916be6611850fca61afd490d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/ec/system76/ec/Kconfig M src/ec/system76/ec/acpi/s76.asl 2 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/87068/1 diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig index 4b71912..f0702a7 100644 --- a/src/ec/system76/ec/Kconfig +++ b/src/ec/system76/ec/Kconfig @@ -6,16 +6,22 @@ System76 EC config EC_SYSTEM76_EC_BAT_THRESHOLDS - depends on EC_SYSTEM76_EC bool default y + depends on EC_SYSTEM76_EC + +config EC_SYSTEM76_EC_FAN2 + bool + default n + depends on EC_SYSTEM76_EC config EC_SYSTEM76_EC_DGPU - depends on EC_SYSTEM76_EC bool default n + select EC_SYSTEM76_EC_FAN2 + depends on EC_SYSTEM76_EC config EC_SYSTEM76_EC_OLED - depends on EC_SYSTEM76_EC bool default n + depends on EC_SYSTEM76_EC diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl index 06000a4..f3e2dec 100644 --- a/src/ec/system76/ec/acpi/s76.asl +++ b/src/ec/system76/ec/acpi/s76.asl @@ -126,9 +126,14 @@ // Fan names Method (NFAN, 0, Serialized) { Return (Package() { - "CPU fan", #if CONFIG(EC_SYSTEM76_EC_DGPU) + "CPU fan", "GPU fan", +#elif CONFIG(EC_SYSTEM76_EC_FAN2) + "fan1", + "fan2", +#else + "CPU fan", #endif }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/87068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I553deefea374b9dd916be6611850fca61afd490d Gerrit-Change-Number: 87068 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Compute total L3 cache size
by Naresh Solanki (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Angel Pons, Felix Held. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Compute total L3 cache size ...................................................................... Patch Set 9: (11 comments) Patchset: PS9: Will rebase on top of CB:85638 (which might have some follow-up changes for Kconfig) & update the current patch with the comments addressed. Commit Message: https://review.coreboot.org/c/coreboot/+/85640/comment/1662f42f_263e4b85?us… : PS9, Line 22: > maybe also point out that this also covers the case of l3 cache blocks having different sizes? Sure. File src/soc/amd/glinda/cpu.c: PS9: > since glinda won't be the only amd soc where this is needed, please consider moving the implementati […] ack https://review.coreboot.org/c/coreboot/+/85640/comment/0ac68754_08ace06f?us… : PS9, Line 22: get > i'd use a different word than 'get' here, since my expectation from a function where the name contai […] ack https://review.coreboot.org/c/coreboot/+/85640/comment/5e033c05_09c76362?us… : PS9, Line 24: 0x8000001e > CPUID_EBX_CORE_ID ack https://review.coreboot.org/c/coreboot/+/85640/comment/da011696_bdc33deb?us… : PS9, Line 24: cpuid > since we only need the data in ebx, i'd use cpuid_ebx instead of cpuid here ack https://review.coreboot.org/c/coreboot/+/85640/comment/c6b29ef9_a79978d0?us… : PS9, Line 27: uint8_t level = 3; > this could be made const ack https://review.coreboot.org/c/coreboot/+/85640/comment/ad211480_82241613?us… : PS9, Line 27: 3 > CACHE_L3 ack https://review.coreboot.org/c/coreboot/+/85640/comment/c5377c7b_713f94d0?us… : PS9, Line 38: 3 > CACHE_L3 ack https://review.coreboot.org/c/coreboot/+/85640/comment/1c668b50_7df0b422?us… : PS9, Line 49: for (int i = 0; i < get_cpu_count(); i++) { > a comment on this for loop might make it a bit easier to understand. […] ack https://review.coreboot.org/c/coreboot/+/85640/comment/9120518f_53f027d1?us… : PS9, Line 59: } > i'd add a newline here ack -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Apr 2025 16:45:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

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[S] Change in coreboot[main]: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Ben Kao, Dinesh Gehlot, Dtrain Hsu, Intel coreboot Reviewers, Jamie Chen, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Jérémy Compostella has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/87033?usp=email ) Change subject: mb/var/uldrenite: Configure descriptor for either MBVR or FIVR ...................................................................... Patch Set 6: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87033/comment/79d133ed_dcb7ffeb?us… : PS6, Line 9: R( nit: space https://review.coreboot.org/c/coreboot/+/87033/comment/9cb91577_a15dcdd4?us… : PS6, Line 10: ( nit: space File src/mainboard/google/brya/variants/uldrenite/variant.c: https://review.coreboot.org/c/coreboot/+/87033/comment/607db58b_95f12593?us… : PS6, Line 3: #include <baseboard/gpio.h> : #include <baseboard/variants.h> : #include <console/console.h> : #include <delay.h> : #include <fw_config.h> : #include <sar.h> : #include <soc/bootblock.h> : #include <boardid.h> nit: Not a strong rule, but usually headers are alphabetically sorted. It seems it was before your change, so I would recommend you do the same. https://review.coreboot.org/c/coreboot/+/87033/comment/d94d3f3b_1199c5ab?us… : PS6, Line 85: .* space https://review.coreboot.org/c/coreboot/+/87033/comment/28ff8b87_fb403f3e?us… : PS6, Line 91: } space https://review.coreboot.org/c/coreboot/+/87033/comment/5882d928_8d1dd57c?us… : PS6, Line 96: } space File src/soc/intel/alderlake/bootblock/update_descriptor.c: https://review.coreboot.org/c/coreboot/+/87033/comment/f1def584_2aafa9f8?us… : PS6, Line 26: if (read32p((uintptr_t)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { : printk(BIOS_ERR, "Flash Descriptor is not valid\n"); : return false; : } : : /* Check host has write access to the Descriptor Region */ : if (!((read32p((uintptr_t)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { : printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); : return false; : } Why is this necessary? -- To view, visit https://review.coreboot.org/c/coreboot/+/87033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Gerrit-Change-Number: 87033 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ben Kao <ben.kao(a)intel.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 16:37:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Naresh Solanki (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Andy Ebrahiem, Angel Pons, Felix Held, Jincheng Li, Jérémy Compostella, Maximilian Brune, Patrick Rudolph, Shuo Liu. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... Patch Set 7: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/85638/comment/f79c8b50_32919613?us… : PS7, Line 215: bool __weak soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) > hmm, i wonder if it would be better to have a kconfig option to replace the common implementation by […] I wrote it in this because I felt it is easy for various SoC vendors to easily chip in custom handler. But I'm aligned with whatever best that works for our coreboot community. Sure thing that I can add a Kconfig(say CONFIG_SOC_FILL_CPU_CACHE_INFO). I guess you meant something like: ``` bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) { if (!info) return false; if (CONFIG(SOC_FILL_CPU_CACHE_INFO)) return soc_fill_cpu_cache_info(level, info); else return x86_get_cpu_cache_info(level, info); } ``` Let me know if above way works. I'll align the follow-up patch accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: NyeonWoo Kim Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Apr 2025 16:34:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements
by Sean Rhodes (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/87067?usp=email ) Change subject: mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie21a873ad7af1504f46db769c3abba00c0e61008 Gerrit-Change-Number: 87067 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 15:44:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements
by Matt DeVillier (Code Review) 01 Apr '25

01 Apr '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87067?usp=email ) Change subject: mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements ...................................................................... mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements The byte_adl is an Alderlake board, so we don't need to do any SoC checks to determine which CFR elements to include. TEST=build/boot starlabs/byte_adl, verify CFR options unchanged. Change-Id: Ie21a873ad7af1504f46db769c3abba00c0e61008 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/cfr.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/87067/1 diff --git a/src/mainboard/starlabs/byte_adl/cfr.c b/src/mainboard/starlabs/byte_adl/cfr.c index 81d74b9..442326f 100644 --- a/src/mainboard/starlabs/byte_adl/cfr.c +++ b/src/mainboard/starlabs/byte_adl/cfr.c @@ -38,14 +38,12 @@ SM_ENUM_VALUE_END }, }); -#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) static const struct sm_object gna = SM_DECLARE_BOOL({ .opt_name = "gna", .ui_name = "Gaussian & Neural Accelerator", .ui_helptext = "Enable or Disable the Gaussian & Neural Accelerator", .default_value = false, }); -#endif static const struct sm_object me_state = SM_DECLARE_ENUM({ .opt_name = "me_state", @@ -84,7 +82,6 @@ SM_ENUM_VALUE_END }, }); -#if CONFIG(SOC_INTEL_ALDERLAKE) static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({ .opt_name = "pciexp_aspm", .ui_name = "PCI ASPM", @@ -124,7 +121,6 @@ { "L1.2", L1_SS_L1_2 }, SM_ENUM_VALUE_END }, }); -#endif static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({ .opt_name = "reboot_counter", @@ -169,9 +165,7 @@ static struct sm_obj_form devices = { .ui_name = "Devices", .obj_list = (const struct sm_object *[]) { - #if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE) &gna, - #endif NULL }, }; @@ -179,11 +173,9 @@ static struct sm_obj_form pci = { .ui_name = "PCI", .obj_list = (const struct sm_object *[]) { - #if CONFIG(SOC_INTEL_ALDERLAKE) &pciexp_clk_pm, &pciexp_aspm, &pciexp_l1ss, - #endif NULL }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/87067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie21a873ad7af1504f46db769c3abba00c0e61008 Gerrit-Change-Number: 87067 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: move NC pin to default
by Pranava Y N (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Mac Chiang. Pranava Y N has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87062?usp=email ) Change subject: mb/google/fatcat/var/francka: move NC pin to default ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87062?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c594f68b151f8c8c58e35a0590be15456f54b32 Gerrit-Change-Number: 87062 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 15:35:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode"
by Maximilian Brune (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87066?usp=email ) Change subject: Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode" ...................................................................... Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode" This reverts commit 4b5a490b6f3faffe1880c731b50d1a4adabfb622. Reason for revert: This effort was apparently given up on since 4 years. So remove the function, since it is not used at the moment. If someone wants to bring that effort back to live, said person can feel free to do so. Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/cpu/Makefile.mk M src/include/cpu/amd/microcode.h M src/soc/amd/common/block/cpu/update_microcode.c 3 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/87066/1 diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk index 0afe454..2ab8727 100644 --- a/src/cpu/Makefile.mk +++ b/src/cpu/Makefile.mk @@ -59,12 +59,7 @@ cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode -# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -cpu_microcode_blob.bin-align := 64 -else cpu_microcode_blob.bin-align := 16 -endif ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index b6b158c..96cac59 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -7,6 +7,5 @@ void amd_load_microcode_from_cbfs(void); void amd_free_microcode(void); void amd_apply_microcode_patch(void); -void preload_microcode(void); #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 14c4f36..e80339b 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -119,16 +119,3 @@ ucode = NULL; } } - -void preload_microcode(void) -{ - if (!CONFIG(CBFS_PRELOAD)) - return; - - char name[] = CPU_MICROCODE_BLOB_NAME; - uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); - - snprintf(name, sizeof(name), CPU_MICROCODE_BLOB_FORMAT, equivalent_processor_rev_id); - printk(BIOS_DEBUG, "Preloading microcode %s\n", name); - cbfs_preload(name); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/87066?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae Gerrit-Change-Number: 87066 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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