coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
by Matt DeVillier (Code Review) 02 Apr '25

02 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email ) Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING ...................................................................... mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING According to the analysis results, resetting the DSI DPHY to default during a warm boot is needed if 'You are in developer mode' needs to be displayed on the screen in a system using the MIPI-DSI panel. DPHY_0_CLOCK_LANE_TIMING -- address:0x162180, size: 32 bits [31]: CLK_PREPARE Override. 0:HW maintains, 1:SW overrides [30..28]: CLK_PREPARE [27]: CLK_ZERO Override. 0:HW maintains, 1:SW overrides [23..20]: CLK_ZERO [19]: CLK_PRE Override. 0:HW maintains, 1:SW overrides [17..16]: CLK_PRE [15]: CLK_POST Override. 0:HW maintains, 1:SW overrides [10..8]: CLK_POST [7]: CLK_TRAIL Override. 0:HW maintains, 1:SW overrides [2..0]: CLK_TRAIL BUG=b:397805262 TEST=Able to show 'You are in developer mode' Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Signed-off-by: Gareth Yu <gareth.yu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86838 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/meliks/Makefile.mk A src/mainboard/google/brya/variants/meliks/ramstage.c 2 files changed, 57 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/meliks/Makefile.mk b/src/mainboard/google/brya/variants/meliks/Makefile.mk index bc560b8..3036518 100644 --- a/src/mainboard/google/brya/variants/meliks/Makefile.mk +++ b/src/mainboard/google/brya/variants/meliks/Makefile.mk @@ -5,3 +5,4 @@ ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/meliks/ramstage.c b/src/mainboard/google/brya/variants/meliks/ramstage.c new file mode 100644 index 0000000..d2a9b5c --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/ramstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ + +#include <soc/ramstage.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/mmio.h> + +#define DPHY_0_CLOCK_LANE_TIMING 0x162180 +#define RESET_DPHY_0_CLOCK_LANE_TIMING 0 + +static uint32_t igd_mem_base(void) +{ + uint32_t igd_bar = pci_read_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0); + + /* Check if the controller is disabled or not present */ + if (igd_bar == 0 || igd_bar == 0xffffffff) + return 0; + + return (igd_bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +static void igd_set_mem_base(uint32_t base) +{ + uint16_t igd_cmd; + + pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, base); + igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND); + pci_write_config16(SA_DEVFN_IGD, PCI_COMMAND, igd_cmd | PCI_COMMAND_MEMORY); +} + +static void reset_display_dphy_clock(void) +{ + uint32_t igd_base = igd_mem_base(); + bool need_temp_bar = false; + + if (!igd_base) { + need_temp_bar = true; + igd_base = CONFIG_GFX_GMA_DEFAULT_MMIO; + igd_set_mem_base(igd_base); + } + + write32p(igd_base + DPHY_0_CLOCK_LANE_TIMING, RESET_DPHY_0_CLOCK_LANE_TIMING); + + if (need_temp_bar) + igd_set_mem_base(0); +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* DPHY CLK timing is not reset if the boot reason is warm boot. Hence to make + the function consistent relies on software forcing the DPHY CLK timing to + the HW default */ + reset_display_dphy_clock(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7857c4f71fc7d1d0c5069a462bdd70c8dbb78179 Gerrit-Change-Number: 86838 Gerrit-PatchSet: 30 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.com> Gerrit-Reviewer: Gareth Yu <gareth.yu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: docs/security/vboot: Update supported board list
by Matt DeVillier (Code Review) 02 Apr '25

02 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87029?usp=email ) Change subject: docs/security/vboot: Update supported board list ...................................................................... docs/security/vboot: Update supported board list Generated by util/vboot_list/vboot_list.sh. Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/security/vboot/list_vboot.md 1 file changed, 22 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index bf6fcc0..14a6a23 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -7,6 +7,7 @@ - BirmanPlus for Phoenix SoC - BirmanPlus for Glinda SoC - Chausie +- Crater for Renoir SoC - Majolica - Mayan for Phoenix SoC @@ -54,6 +55,7 @@ - Craaskov - Constitution - Crota +- Dirks - Dochi - Domika - Felwinter @@ -63,6 +65,7 @@ - Gladios - Glassway - Gothrax +- Guren - Hades - Kano - Kinox @@ -72,6 +75,7 @@ - Marasov - Mithrax - Moli +- Moxie - Nivviks - Nereid - Nokris @@ -80,7 +84,9 @@ - Pirrha - Primus - Pujjo +- Pujjoniru - Quandiso +- Quandiso2 - Redrix - Redrix4ES - Riven @@ -111,6 +117,7 @@ - Pujjogatwin - Orisa - Telith +- Meliks - Butterfly (HP Pavilion Chromebook 14) - Cherry - Dojo @@ -129,6 +136,7 @@ - Veluza - Starmie - Wugtrio +- Wyrdeer - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) @@ -230,6 +238,7 @@ - Oak - Elm (Acer Chromebook R13) - Hana (Lenovo N23 Yoga Chromebook) +- Ocelot - Parrot (Acer C7/C710 Chromebook) - Atlas (Google Pixelbook Go) - Poppy @@ -238,18 +247,18 @@ - Nocturne (Google Pixel Slate) - Rammus - Soraka (HP Chromebook x2) -- Ambassador -- Dooly +- Ambassador (Meet Compute System [Intel 10th Gen]) +- Dooly (HP Chromebase 21.5) - Duffy Legacy (32MB) - Duffy (ASUS Chromebox 4) - Faffy (ASUS Fanless Chromebox) -- Genesis +- Genesis (Meet Compute System - Series One [Intel 10th Gen]) - Kaisa Legacy (32MB) - Kaisa (Acer Chromebox CXI4) -- Moonbuggy +- Moonbuggy (Series One Board 65) - Noibat (HP Chromebox G3) - Puff -- Scout +- Scout (Series One Desk 27) - Wyvern (CTL Chromebox CBx2) - Hylia - Navi @@ -373,6 +382,7 @@ - Meteorlake-P RVP with Chrome EC for Prod Silicon - Meteorlake-P RVP with Chrome EC for non-Prod Silicon - Meteorlake-P RVP with Microchip EC +- Ptlrvp - shadowmountain - Strago - Tigerlake UP3 RVP @@ -417,6 +427,10 @@ - PRO Z790-P (WIFI) DDR4 - PRO Z790-P (WIFI) +## NovaCustom +- V540TU (14\") +- V560TU (16\") + ## OpenCellular - Elgon (GBCv2) @@ -447,8 +461,11 @@ - Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7) - Star Labs StarBook Mk VI (i3-1220P and i7-1260P) - Star Labs StarBook Mk VI (i3-1315U and i7-1360P) +- Star Labs StarBook Mk VII (N200) +- Star Labs StarBook Mk VII (165H) - Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H) - Star Labs Lite Mk V (N200) +- Star Labs Lite Mk V Smart Battery (N200) ## Supermicro - X11SSH-TF -- To view, visit https://review.coreboot.org/c/coreboot/+/87029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I079e02d24671a76520587b03a9d83fdc9f33e55b Gerrit-Change-Number: 87029 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs
by Filip Lewiński (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Filip Lewiński, Intel coreboot Reviewers, Michał Kopeć, Paul Menzel. Filip Lewiński has uploaded a new patch set (#5) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83727?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs ...................................................................... soc/intel/cannonlake: Hook up Intel TXT FSP UPDs Set necessary parameters so that FSP can call BIOS ACM ACHECK after MRC. It is required to perform ACHECK in certain conditions and the Intel TXT will not function properly without calling it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled. Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/Makefile.mk M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83727/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d Gerrit-Change-Number: 83727 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: commonlib/storage: Include pci_def.h
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87092?usp=email ) Change subject: commonlib/storage: Include pci_def.h ...................................................................... Patch Set 2: (1 comment) File src/commonlib/storage/pci_sdhci.c: https://review.coreboot.org/c/coreboot/+/87092/comment/bca0a708_f17ae012?us… : PS2, Line 5: #include <device/pci_def.h> > > This is already part of above header when CONFIG_PCI is enabled. > > The addition of pci_sdhci.c without depending on CONFIG_PCI causes issues when PCI kconfig is disabled, resulting in missing macro errors during compilation. > > ``` > src/commonlib/storage/Makefile.mk:22:bootblock-y += pci_sdhci.c > src/commonlib/storage/Makefile.mk:27:verstage-y += pci_sdhci.c > src/commonlib/storage/Makefile.mk:32:romstage-y += pci_sdhci.c > src/commonlib/storage/Makefile.mk:37:postcar-y += pci_sdhci.c > src/commonlib/storage/Makefile.mk:42:ramstage-y += pci_sdhci.c > ``` Especially when `COMMONLIB_STORAGE` and other storage Kconfigs are selected without PCI Kconfig, we should see this issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/87092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7 Gerrit-Change-Number: 87092 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Apr 2025 15:49:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: commonlib/storage: Include pci_def.h
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87092?usp=email ) Change subject: commonlib/storage: Include pci_def.h ...................................................................... Patch Set 2: (1 comment) File src/commonlib/storage/pci_sdhci.c: https://review.coreboot.org/c/coreboot/+/87092/comment/73f68a9c_16eb6567?us… : PS2, Line 5: #include <device/pci_def.h> > This is already part of above header when CONFIG_PCI is enabled. The addition of pci_sdhci.c without depending on CONFIG_PCI causes issues when PCI kconfig is disabled, resulting in missing macro errors during compilation. ``` src/commonlib/storage/Makefile.mk:22:bootblock-y += pci_sdhci.c src/commonlib/storage/Makefile.mk:27:verstage-y += pci_sdhci.c src/commonlib/storage/Makefile.mk:32:romstage-y += pci_sdhci.c src/commonlib/storage/Makefile.mk:37:postcar-y += pci_sdhci.c src/commonlib/storage/Makefile.mk:42:ramstage-y += pci_sdhci.c ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/87092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7 Gerrit-Change-Number: 87092 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Apr 2025 15:45:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[L] Change in coreboot[main]: mb/starlabs/starbook: Simplify CFR options
by Matt DeVillier (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Sean Rhodes. Hello Sean Rhodes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87088?usp=email to look at the new patch set (#3). Change subject: mb/starlabs/starbook: Simplify CFR options ...................................................................... mb/starlabs/starbook: Simplify CFR options Move declaration of all CFR objects to a header file, so they don't need to be guarded. Simplify the enablement of CFR options by creating board-level Kconfig options as needed. TEST=build/boot starbook MTL, TGL, ADL-N. Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/cfr.c A src/mainboard/starlabs/starbook/cfr.h 3 files changed, 229 insertions(+), 202 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/87088/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf Gerrit-Change-Number: 87088 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: commonlib/storage: Include pci_def.h
by Kapil Porwal (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jayvik Desai, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87092?usp=email ) Change subject: commonlib/storage: Include pci_def.h ...................................................................... Patch Set 2: (1 comment) File src/commonlib/storage/pci_sdhci.c: https://review.coreboot.org/c/coreboot/+/87092/comment/dfc95ad3_d74fda4d?us… : PS2, Line 5: #include <device/pci_def.h> This is already part of above header when CONFIG_PCI is enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/87092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7 Gerrit-Change-Number: 87092 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Apr 2025 15:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: security/vboot: Add option for enabling ADB over network via GBB flag
by Raul Rangel (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jon Murphy, Julius Werner, Kapil Porwal, Subrata Banik, Yu-Ping Wu. Raul Rangel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87031?usp=email ) Change subject: security/vboot: Add option for enabling ADB over network via GBB flag ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I didn't read the whole chain, but I'm working on trying to drop this GBB flag. > My goal is to keep ADB over network default enabled for fatcat AP FW serial image (which is often used for debugging purpose) We can land a change to the fatcat OS configs to enable insecure ADB by default. You are still early on, and won't be dogfooding anytime soon, so there shouldn't be any push back. -- To view, visit https://review.coreboot.org/c/coreboot/+/87031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3a69f20ae39baf482a748a00556268d0d0aef7 Gerrit-Change-Number: 87031 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 02 Apr 2025 15:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Tidy GPIO comments for the Keyboard
by Matt DeVillier (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87122?usp=email ) Change subject: mb/starlabs/starlite_adl: Tidy GPIO comments for the Keyboard ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icfb80295ba0c55184b174a63756e8779111d9b76 Gerrit-Change-Number: 87122 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Apr 2025 14:54:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Disconnect unused GPIO
by Matt DeVillier (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87121?usp=email ) Change subject: mb/starlabs/starlite_adl: Disconnect unused GPIO ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a8fb34837b1b3f2f066ccc260f0ab749d7782c0 Gerrit-Change-Number: 87121 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 02 Apr 2025 14:54:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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