coreboot-gerrit April 2025

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add Touch Controller UPD and SoC config
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) ( 35 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Add Touch Controller UPD and SoC config ...................................................................... soc/intel/pantherlake: Add Touch Controller UPD and SoC config This commit introduces the necessary changes to configure the Touch Host Controller User Platform Data (UPD) fields such as ThcAssignment, ThcMode, and ThcWakeOnTouch according to the specific SoC chip configuration derived from the devicetree. Key changes include: - Creation of override functions to supply SoC-specific configurations for the Touch Host Controller (THC). - Addition of a new SoC-specific THC header file. - Inclusion of a motherboard (MB)-specific THC header file. - Establishment of a build path to allow devicetree to leverage variant-specific defines. BUG=none TEST=Add CONFIG_DRIVERS_INTEL_TOUCH to fatcat board with the devicetree changes for touchscreen and/or touchpad, as well as proper CBI settings. Boot the board to OS and check that the THC SoC-specific info is generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/85199 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/Makefile.mk M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/include/soc/touch.h A src/soc/intel/pantherlake/touch.c 5 files changed, 134 insertions(+), 2 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index f3403b5..e2f8dd7 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -43,6 +43,7 @@ ramstage-y += systemagent.c ramstage-y += tcss.c ramstage-y += xhci.c +ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c smm-y += elog.c smm-y += gpio.c diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index cd91e31..eb702b7 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -26,6 +26,8 @@ #define MAX_SAGV_POINTS 4 #define MAX_HD_AUDIO_SDI_LINKS 2 +#define NUM_THC 2 + /* In-Band ECC Operation Mode */ enum ibecc_mode { IBECC_MODE_PER_REGION, @@ -539,6 +541,19 @@ uint16_t max_dram_speed_mts; + /* + * Touch Host Controller Mode + * Switch between Intel THC protocol and Industry standard HID protocols. + * 0x0:Thc, 0x1:HID over SPI, 0x2:HID over I2C + */ + uint8_t thc_mode[NUM_THC]; + + /* + * Touch Host Controller Wake On Touch + * Based on this setting vGPIO for given THC will be in native mode, and additional _CRS + * for wake will be exposed in ACPI + */ + bool thc_wake_on_touch[NUM_THC]; }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 7544894..cac866f 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -576,8 +576,15 @@ static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_pantherlake_config *config) { - s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE; - s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE; + for (size_t i = 0; i < NUM_THC; i++) { + if (!is_devfn_enabled(_PCI_DEVFN(THC, i))) { + s_cfg->ThcAssignment[i] = THC_NONE; + continue; + } + s_cfg->ThcAssignment[i] = THC_0 + i; + s_cfg->ThcMode[i] = config->thc_mode[i]; + s_cfg->ThcWakeOnTouch[i] = config->thc_wake_on_touch[i]; + } } static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/pantherlake/include/soc/touch.h b/src/soc/intel/pantherlake/include/soc/touch.h new file mode 100644 index 0000000..33b3d1d --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/touch.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_TOUCH_H_ +#define _SOC_PANTHERLAKE_TOUCH_H_ + +/* For THC-I2C: */ + +/* + * I2C Standard Mode (100Kbps): + * Requested Connection Speed: 186A0 + * I2C Speed Mode: Standard (100Kbps) = 0x186A0 + * + * I2C Fast Mode (400Kbps): + * Requested Connection Speed: 61A80 + * I2C Speed Mode: Fast (400Kbps) = 0x612B0 + * + * I2C Fast-Plus Mode (1Mbps): + * Requested Connection Speed: F4240 + * I2C Speed Mode: Fast-Plus (1Mbps) = 0xF4240 + * FM SCL HIGH Period: 34 Fast Mode (FM) CLK Signal HIGH Period + * FM SCL LOW Period: 3E Fast Mode (FM) CLK Signal LOW Period + */ +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_SM 0x186a0 +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FM 0x61a80 +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FMP 0xf4240 + +/* + * 0 = 7-bit Addressing Mode for HID-I2C (Default) + * 1 = 10-bit Addressing Mode for HID-I2C + */ +#define SOC_PTL_THC_I2C_ADDR_MODE 0 +#define SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD 0x267 +#define SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD 0x271 +#define SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD 0x92 +#define SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD 0x9c +#define SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP 0 +#define SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD 0x34 +#define SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD 0x3e +#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP 0 + + +/* For THC-SPI: */ + +/* unit: ms */ +#define SOC_PTL_THC_RST_SEQ_DLY 300 + +/* The initial default speed is 17000000 Hz. */ +#define SOC_PTL_THC_CONNECTION_SPEED 17000000 + +/* 0 = no limit */ +#define SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ 0 +#define SOC_PTL_THC_PERFORMANCE_LIMIT 0 + +#endif /* _SOC_PANTHERLAKE_TOUCH_H_ */ diff --git a/src/soc/intel/pantherlake/touch.c b/src/soc/intel/pantherlake/touch.c new file mode 100644 index 0000000..ed475fe --- /dev/null +++ b/src/soc/intel/pantherlake/touch.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/touch/chip.h> +#include <soc/touch.h> + +/* SoC-specific THC-I2C config */ +const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void) +{ + static const struct intel_thc_hidi2c_info soc_thc_hidi2c_info = { + .connection_speed = SOC_PTL_THC_I2C_CONNECTION_SPEED_FM, + .addr_mode = SOC_PTL_THC_I2C_ADDR_MODE, + .sm_scl_high_period = SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD, + .sm_scl_low_period = SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD, + .sm_sda_hold_tx_period = SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD, + .sm_sda_hold_rx_period = SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD, + .fm_scl_high_period = SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD, + .fm_scl_low_period = SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD, + .fm_sda_hold_tx_period = SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD, + .fm_sda_hold_rx_period = SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_s_f_fp = SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP, + .fmp_scl_high_period = SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD, + .fmp_scl_low_period = SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD, + .fmp_sda_hold_tx_period = SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD, + .fmp_sda_hold_rx_period = SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD, + .hm_scl_high_period = SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD, + .hm_scl_low_period = SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD, + .hm_sda_hold_tx_period = SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD, + .hm_sda_hold_rx_period = SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_h_fp = SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP, + }; + return &soc_thc_hidi2c_info; +} + +/* SoC-specific THC-SPI config */ +const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void) +{ + static const struct intel_thc_hidspi_info soc_thc_hidspi_info = { + .connection_speed = SOC_PTL_THC_CONNECTION_SPEED, + .write_mode = HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI, + .limit_packet_size = SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ, + .performance_limit = SOC_PTL_THC_PERFORMANCE_LIMIT, + .reset_sequencing_delay = SOC_PTL_THC_RST_SEQ_DLY, + }; + return &soc_thc_hidspi_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/touch/touch.c: https://review.coreboot.org/c/coreboot/+/87085/comment/540c8eb1_cea95d98?us… : PS1, Line 197: /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode > Missing line break before NOTE. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:51:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella. Hello Intel coreboot Reviewers, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87085?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 --- M src/drivers/intel/touch/touch.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87085/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85200?usp=email ) Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... Patch Set 37: (3 comments) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/85200/comment/085a363f_566526f1?us… : PS26, Line 483: PAD_CFG_GPI_APIC_DRIVER > It is not because it is vGPIO. […] marked as resolved. File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85200/comment/f295c042_a77bc73a?us… : PS26, Line 333: GPE0_DW0_10 > Yes, GpioInt() is created for wake_gpio which will work in Driver mode. […] You are right about wake_gpe. Only when using Interrupt() in _CRS, the GPE event is used and need the GPE mapping bit in _PRW method. Also, the GPIO pad needs to be in ACPI mode. Currently, we use GpioInt() and PAD in Driver mode for THC. For touchpad in LPSS mode, we will still need to remap pmc_gpe0_dw0 to GPP_F group. The i2c generic driver uses _PRW and GPE. I removed the pmc_gpe0_dw0 override for vGPIO. Thanks for pointing this out. This is very helpful. File src/mainboard/google/fatcat/variants/fatcat/variant.c: https://review.coreboot.org/c/coreboot/+/85200/comment/dc771f38_70994455?us… : PS29, Line 33: if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) : config->thc_mode[0] = THC_HID_I2C_MODE; : else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) : config->thc_mode[0] = THC_HID_SPI_MODE; : else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) > It is a bit complicated on Fatcat board constraint regarding of overriding pmc_gpe0_dw0. […] removed the override for pmc_gpe0_dw0 to vGPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:47:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers. Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/drivers/intel/touch/touch.c: https://review.coreboot.org/c/coreboot/+/87085/comment/d0c47343_7cf931ab?us… : PS1, Line 197: /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode Missing line break before NOTE. -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Intel coreboot Reviewers. Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 --- M src/drivers/intel/touch/touch.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87085/1 diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c index 0283312..f094683 100644 --- a/src/drivers/intel/touch/touch.c +++ b/src/drivers/intel/touch/touch.c @@ -194,14 +194,19 @@ touch_acpi_name(dev)); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); + /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode + * config->wake_irq: uses Interrupt() in _CRS; use GPE; PAD needs to be ACPI Mode + */ if (config->wake_gpio.pin_count) acpi_device_write_gpio(&config->wake_gpio); else if (config->wake_irq.pin) acpi_device_write_interrupt(&config->wake_irq); acpigen_write_resourcetemplate_footer(); - acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); - acpigen_write_PRW(config->wake_gpe, 3); + if (config->wake_irq.pin) { + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); + acpigen_write_PRW(config->wake_gpe, 3); + } } static void touch_generate_acpi_i2cdev_dsd(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik, Wonkyu Kim. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85200?usp=email to look at the new patch set (#37). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad This commit introduces support for touch functionalities on the Google Fatcat board( Please see docu # 818597). Changes include: - Configuration for building with the THC driver - Support for touchscreen devices in both THC-I2C and THC-SPI modes - Rework is necessary for touchscreen use in THC-SPI mode on Fatcat board - The ELAN BOM37A device is supported in THC-I2C mode - The ELAN BOM36 device is supported in THC-SPI mode - Support for the HYNITRON HFW68H touchpad device in THC-I2C mode - A rework is required to switch the interrupt pad from GPP_A13 to GPP_F18 for touchpad use in THC-I2C mode - Introduction of variant-specific touch.h header file - Wake support from S0ix state for both touchscreen and touchpad across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI - PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in variant.c for wake support BUG=none TEST= 1. Set the CBI firmware configuration for touchscreen to TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C 2. Check the ACPI objects are generated in SSDT 3. The devices should be enumerated under the /sys/class/hidraw directory 4. The Touchscreen and/or touchpad should function properly The cursor on the screen should move accordingly 5. Test wake from S0ix state via touchscreen and touchpad inputs 6. Repeat the above for the THC CBI configurations: touchscreen: TOUCHSCREEN_THC_I2C touchpad: TOUCHPAD_THC_I2C Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/fatcat/variant.c 5 files changed, 183 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85200/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Set CNVi strap to disabled
by Matt DeVillier (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87084?usp=email ) Change subject: mb/starlabs/starbook/adl_n: Set CNVi strap to disabled ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82f3ce699d5e823e1ce942acb7a0ba1bd548d9a0 Gerrit-Change-Number: 87084 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 01 Apr 2025 20:44:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 01 Apr '25

01 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87083?usp=email ) Change subject: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87083/comment/38ab2c2f_88662b6c?us… : PS1, Line 9: connected. > line wrap Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I779b6bc486b68e8df50347540364901507a7102c Gerrit-Change-Number: 87083 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 20:44:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87083?usp=email to look at the new patch set (#2). Change subject: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs ...................................................................... mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I779b6bc486b68e8df50347540364901507a7102c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/87083/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I779b6bc486b68e8df50347540364901507a7102c Gerrit-Change-Number: 87083 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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