coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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410 discussions

[S] Change in coreboot[main]: mb/google/fatcat: Allow board-specific FSP-M UPD override
by Pranava Y N (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Subrata Banik, Wonkyu Kim. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87089?usp=email ) Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Gerrit-Change-Number: 87089 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 03 Apr 2025 04:42:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Enable early EC software sync for Rull
by Pranava Y N (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/87104?usp=email ) Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/87104/comment/52835861_fe82da4b?us… : PS2, Line 563: VBOOT_EARLY_EC_SYNC > select this inside vboot section with board Kconfig name Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Gerrit-Change-Number: 87104 Gerrit-PatchSet: 3 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Apr 2025 04:33:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Enable early EC software sync for Rull
by Pranava Y N (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87104?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull ...................................................................... mb/google/nissa/var/rull: Enable early EC software sync for Rull Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software sync in romstage. This is useful to achieve full USB-PD negotiation early in the boot flow. It eliminates a problem seen in rull devices where PMC is wrongly configured in depthcharge during the EC-sync scenario which prevents USB devices from getting detected when connected via a self-powered USB hub. BUG=b:386920751 TEST=Verify detection and booting to OS from USB drive connected to the Servo v4 debugger (self-powered hub) during the EC-sync scenario. Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/87104/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Gerrit-Change-Number: 87104 Gerrit-PatchSet: 3 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Allow board-specific FSP-M UPD override
by Sowmya Aralguppe (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, Wonkyu Kim. Sowmya Aralguppe has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87089?usp=email ) Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Gerrit-Change-Number: 87089 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 03 Apr 2025 03:55:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat: Allow board-specific FSP-M UPD override
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Sowmya Aralguppe, Wonkyu Kim. Hello Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87089?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Code-Review+1 by Wonkyu Kim, Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override ...................................................................... mb/google/fatcat: Allow board-specific FSP-M UPD override This commit introduces a mechanism to allow mainboards to override the default FSP-M UPDs for Panther Lake. - Adds `variant_update_soc_memory_init_params` as a weak function in `variants.h` and `romstage.c` for board-specific implementations. - In `romstage.c`, `mainboard_memory_init_params` now calls `variant_update_soc_memory_init_params` to apply board-specific overrides to the FSP-M UPDs. This enables finer-grained control over memory initialization parameters at the variant level. BUG=b:328770565 TEST=Able to build and boot google/fatcat. Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/romstage.c M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/87089/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Gerrit-Change-Number: 87089 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Allow board-specific FSP-M UPD override
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Pranava Y N, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87089?usp=email ) Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87089/comment/d00dc302_6884945f?us… : PS2, Line 22: TEST=Able to reduce the boot time by 18ms. > Does that test really apply to this CL ? Acknowledged File src/mainboard/google/fatcat/romstage.c: https://review.coreboot.org/c/coreboot/+/87089/comment/34b0991f_37e51016?us… : PS2, Line 22: d > Nit: Default […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Gerrit-Change-Number: 87089 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 03 Apr 2025 03:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: commonlib/storage: Avoid build error when CONFIG_PCI is disabled
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87092?usp=email ) Change subject: commonlib/storage: Avoid build error when CONFIG_PCI is disabled ...................................................................... commonlib/storage: Avoid build error when CONFIG_PCI is disabled When CONFIG_PCI is disabled, but COMMONLIB_STORAGE and COMMONLIB_STORAGE_SD are enabled, the compilation of pci_sdhci.c fails. This is because the code attempts to use pci_s_read_config32() with the PCI_BASE_ADDRESS_0 macro, which are only defined when CONFIG_PCI is enabled. Add an early return NULL check based on !CONFIG(PCI) at the beginning of new_pci_sdhci_controller(). This prevents the compiler from attempting to process the PCI-specific code path when PCI support is not configured, resolving the build failure in this specific Kconfig scenario. TEST=Able to build herobrine. Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87092 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/commonlib/storage/pci_sdhci.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index f7922d4..51b44de 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -2,6 +2,7 @@ #include <commonlib/sdhci.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ops.h> #include <stdint.h> @@ -42,6 +43,9 @@ { uintptr_t addr; + if (!CONFIG(PCI)) + return NULL; + addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0); if (addr == ((uint32_t)~0)) { sdhc_error("Error: PCI SDHCI not found\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/87092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7 Gerrit-Change-Number: 87092 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Directly assign HDA SDI enable
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87109?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Directly assign HDA SDI enable ...................................................................... soc/intel/pantherlake: Directly assign HDA SDI enable The double negation (`!!`) was unnecessarily used when assigning the `pch_hda_sdi_enable` type boolean from the SOC config to the FSP M config. This commit removes the redundant `!!` operator, directly assigning the boolean value of `config->pch_hda_sdi_enable[i]` to `m_cfg->PchHdaSdiEnable[i]`. TEST=Able to build and boot google/fatcat. Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87109 Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Wonkyu Kim: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b5fc93b..521d2f2 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -162,7 +162,7 @@ m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) - m_cfg->PchHdaSdiEnable[i] = !!config->pch_hda_sdi_enable[i]; + m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/87109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a Gerrit-Change-Number: 87109 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Conditionally check for barrel charger
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87064?usp=email ) Change subject: mb/google/fatcat: Conditionally check for barrel charger ...................................................................... mb/google/fatcat: Conditionally check for barrel charger The barrel charger check in `baseboard_devtree_update` was unconditional, increasing boot time on platforms without it. This commit conditions the check on `CONFIG(BOARD_GOOGLE_MODEL_FATCAT)`, making it specific to the fatcat board. This avoids unnecessary delay on platforms like francka and felino. BUG=b:328770565 TEST=Boot time reduced by 56ms. Change-Id: Id7a26b634a1a310f714fbf4b4a2accd75665bc28 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87064 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Kapil Porwal: Looks good to me, approved Jayvik Desai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c index 030b587..21f8ccd 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c @@ -53,7 +53,7 @@ void baseboard_devtree_update(void) { /* Don't optimize the power limit if booting with barrel attached */ - if (google_chromeec_is_barrel_charger_present()) + if (CONFIG(BOARD_GOOGLE_MODEL_FATCAT) && google_chromeec_is_barrel_charger_present()) return; if (!google_chromeec_is_battery_present()) -- To view, visit https://review.coreboot.org/c/coreboot/+/87064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7a26b634a1a310f714fbf4b4a2accd75665bc28 Gerrit-Change-Number: 87064 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim. Hello Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87085?usp=email to look at the new patch set (#4). Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 --- M src/drivers/intel/touch/touch.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87085/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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coreboot-gerrit April 2025