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Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
......................................................................
mb/google/fatcat: …
[View More]Disable EnableFastVmode on Panther Lake H SoC
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program Panther Lake U IccLimit on
FastVMode capable boards, causing performance degradation under
high-stress conditions. By also disabling EnableFastVmode, the I_TRIP
value is prevented from being set lower than the device's actual
capability.
TEST=Verify that IccLimit is programmed with FSP default values.
Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/fatcat/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87505/4
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Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
......................................................................
mb/google/fatcat: …
[View More]Disable EnableFastVmode on Panther Lake H SoC
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program Panther Lake U IccLimit on
FastVMode capable boards, causing performance degradation under high-stress
conditions. By also disabling EnableFastVmode, the I_TRIP value is
prevented from being set lower than the device's actual capability.
TEST=Verify that IccLimit is programmed with FSP default values.
Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/fatcat/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87505/3
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
......................................................................
mb/google/fatcat: …
[View More]Disable EnableFastVmode on Panther Lake H SoC
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program IccLimit, causing
performance degradation under high-stress conditions. By also disabling
EnableFastVmode, the I_TRIP value is prevented from being set lower than
the device's actual capability.
TEST=Verified that IccLimit limit is not programmed at all in the FSP
logs.
Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/fatcat/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87505/2
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Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
......................................................................
mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was …
[View More]discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program IccLimit, causing performance
degradation under high-stress conditions. By also disabling
EnableFastVmode, the I_TRIP value is prevented from being set lower than
the device's actual capability.
TEST=Verified that IccLimit limit is not programmed at all in the FSP logs.
Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/fatcat/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87505/1
diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 44a901a..7a50938 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -62,8 +62,10 @@
* because the I_TRIP value is set lower than the device's actual capability.
*/
printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
- for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
+ for (size_t i = 0; i < NUM_VR_DOMAINS; i++) {
m_cfg->CepEnable[i] = false;
+ m_cfg->EnableFastVmode[i] = false;
+ }
}
void mainboard_memory_init_params(FSPM_UPD *memupd)
--
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87504?usp=email )
Change subject: allocator_v4: Re-enable top-down allocation for edk2
......................................................................
allocator_v4: Re-enable top-down allocation for edk2
Commit a959f0ad7620 ("allocator_v4: Disable top-down allocation for
EDK2") disabled top-down allocation for edk2 due to a bug which broke
display init with Intel IGD. A workaround has been …
[View More]implemented in
MrChromebox's fork (and others) while the issue is being resolved
upstream, so re-enable top-down allocation unless upstream edk2
is being used.
TEST=build/boot various Google mainboards with edk2 payload selected.
Change-Id: I0e9b0d02bbf30878aef37a97d6a743a402700fc7
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/device/Kconfig
1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/87504/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index bfb38b4..e1a8d38 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -994,14 +994,16 @@
config RESOURCE_ALLOCATION_TOP_DOWN
bool "Allocate resources from top down"
- default n if PAYLOAD_EDK2
+ default n if PAYLOAD_EDK2 && EDK2_REPO_OFFICIAL
default y
help
Top-down allocation is required to place resources above 4G by
default (i.e. even when there is still space below). On some
platforms, it might make a difference because of conflicts with
- undeclared resources. EDK2 is currently reported to also have
- problems on some platforms, at least with Intel's IGD.
+ undeclared resources.
+
+ Upstream EDK2 is currently reported to also have problems on some
+ platforms at least with Intel's IGD; MrChromebox's fork works fine.
config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
bool
--
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Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/87499?usp=email )
Change subject: soc/intel/elkhartlake: Hook up S0ix setting to option API
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> didn't test here, was just adding all SoC's which use `s0ix_enable` for …
[View More]completeness. […]
I've moved the config to ramstage since there are no UPDs or other settings which depend on the value of s0ix_enable pre-ramstage
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87503?usp=email )
Change subject: soc/intel/tigerlake: Hook up S0ix setting to option API
......................................................................
soc/intel/tigerlake: Hook up S0ix setting to option API
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: …
[View More]I6c05212eaf004ea74b7fd3fa92cbaa314474b7e9
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/87503/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index c3400b4..35562d1 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -682,6 +682,9 @@
params->SiSkipSsidProgramming = 0;
mainboard_silicon_init_params(params);
+
+ /* Runtime configuration of S0ix */
+ config->s0ix_enable = get_uint_option("s0ix_enable", config->s0ix_enable);
}
/*
--
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The following approvals got outdated and were removed:
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Change subject: soc/intel/pantherlake: Hook up S0ix setting to option API
......................................................................
soc/intel/pantherlake: Hook up S0ix setting to option API
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I22b65ecbf8846577d1bbb69f8ebb32c639b9643f
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/pantherlake/fsp_params.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/87502/3
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Change subject: soc/intel/meteorlake: Hook up S0ix setting to option API
......................................................................
soc/intel/meteorlake: Hook up S0ix setting to option API
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Id9e75020ab359bf94c75ffc1aaaef7af83d4c9c6
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/meteorlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
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Change subject: soc/intel/jasperlake: Hook up S0ix setting to option API
......................................................................
soc/intel/jasperlake: Hook up S0ix setting to option API
Hook up the …
[View More]s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Id35705304e872395ce88617c83d9edecb03b02a1
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---
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