coreboot-gerrit March 2025

coreboot-gerrit@coreboot.org

1 participants
2811 discussions

[XS] Change in coreboot[main]: moxie: Remove wifi sar table for moxie
by Paul Menzel (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Lucas Chen, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by Lucas Chen. ( https://review.coreboot.org/c/coreboot/+/87004?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: moxie: Remove wifi sar table for moxie ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87004/comment/9db100b1_c8748495?us… : PS2, Line 7: for moxie Redundant. https://review.coreboot.org/c/coreboot/+/87004/comment/4a2e0fa0_e30b859c?us… : PS2, Line 7: moxie Please look at `git log --oneline`. -- To view, visit https://review.coreboot.org/c/coreboot/+/87004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I012ff2d9c8c4d6d4480cae7166bf8e633bcaa752 Gerrit-Change-Number: 87004 Gerrit-PatchSet: 2 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 31 Mar 2025 21:09:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add USB host support
by Paul Menzel (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87021?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8189: Add USB host support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87021/comment/1cc3562a_42715c39?us… : PS2, Line 14: TEST=build pass Did you test this? -- To view, visit https://review.coreboot.org/c/coreboot/+/87021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Gerrit-Change-Number: 87021 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 21:08:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Paul Menzel (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Mac Chiang, Naveen M, Pranava Y N, Subrata Banik, Tongtong Pan, Varun Upadhyay, Weimin Wu. Paul Menzel has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85571/comment/f73c2382_c2b8ad24?us… : PS4, Line 9: Update SoundWire driver to support ALC712 audio codec. Sorry, for commenting again. Please describe and elaborate, why lane_mapping_count and audio_mode_count is needed. No other driver seems to use it. https://review.coreboot.org/c/coreboot/+/85571/comment/5f275209_a0f3904c?us… : PS4, Line 14: TEST=emerge-fatcat coreboot I guess, you tested this. Please add the commands how to check that your patch works. -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 4 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 21:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Add support for DMIC0
by Kapil Porwal (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Mac Chiang, Subrata Banik. Kapil Porwal has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/86699?usp=email ) Change subject: mb/google/fatcat/var/francka: Add support for DMIC0 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/francka/fw_config.c: https://review.coreboot.org/c/coreboot/+/86699/comment/36b71123_7692a640?us… : PS6, Line 28: /* GPP_D09: PCH_DGPU_HOLD_RST#_R */ : PAD_NC(GPP_D09, NONE), : /* GPP_D16: HDA_RST# */ : PAD_NC(GPP_D16, NONE), : /* GPP_S00: SNDW_3_SCL */ : PAD_NC(GPP_S00, NONE), : /* GPP_S01: SNDW_3_SDA */ : PAD_NC(GPP_S01, NONE), : /* GPP_S04: SNDW2_CLK */ : PAD_NC(GPP_S04, NONE), : /* GPP_S05: SNDW2_DATA0 */ : PAD_NC(GPP_S05, NONE), > For future SoundWire SKUs, I think it will need to be reconfigured if set to default. Yes but that needs to be handled separately. Currently we can move these GPIOs to gpio.c and later we can define a list of GPIO configuration needed for a sound wire in this file. Note: `gpio_padbased_override` doesn't write to GPIO config registers hence there will be no reconfiguration involved. -- To view, visit https://review.coreboot.org/c/coreboot/+/86699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcc18a6a605694bc5c1a2994453717887814e897 Gerrit-Change-Number: 86699 Gerrit-PatchSet: 6 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 20:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mac Chiang <mac.chiang(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Compute total L3 cache size
by Felix Held (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Angel Pons, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Compute total L3 cache size ...................................................................... Patch Set 9: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85640/comment/bd4c7063_93d5b73f?us… : PS9, Line 22: maybe also point out that this also covers the case of l3 cache blocks having different sizes? File src/soc/amd/glinda/cpu.c: PS9: since glinda won't be the only amd soc where this is needed, please consider moving the implementation to a new c file in soc/amd/common/block/cpu/noncar/. i'd then introduce a new kconfig option and only include the new compilation unit when that's selected and select that kconfig option in the glinda code and only keep the ap_get_l3_cache_sizes call in here. that will allow to easily add this support to other socs that need it too. that kconfig could then also select the kconfig option i suggested adding in CB:85638 https://review.coreboot.org/c/coreboot/+/85640/comment/1de17095_65fd4e0f?us… : PS9, Line 22: get i'd use a different word than 'get' here, since my expectation from a function where the name contains 'get' would be that it returns a return value to the caller. maybe 'ap_stash_l3_cache_sizes'? https://review.coreboot.org/c/coreboot/+/85640/comment/97db6a1f_c40085d5?us… : PS9, Line 24: cpuid since we only need the data in ebx, i'd use cpuid_ebx instead of cpuid here https://review.coreboot.org/c/coreboot/+/85640/comment/2eabba92_115ca1e3?us… : PS9, Line 24: 0x8000001e CPUID_EBX_CORE_ID https://review.coreboot.org/c/coreboot/+/85640/comment/06043141_117f7cc4?us… : PS9, Line 27: uint8_t level = 3; this could be made const https://review.coreboot.org/c/coreboot/+/85640/comment/6860ea80_8719adcb?us… : PS9, Line 27: 3 CACHE_L3 https://review.coreboot.org/c/coreboot/+/85640/comment/3e735c13_7efc44ed?us… : PS9, Line 38: 3 CACHE_L3 https://review.coreboot.org/c/coreboot/+/85640/comment/74cc8ec1_d5c69b12?us… : PS9, Line 49: for (int i = 0; i < get_cpu_count(); i++) { a comment on this for loop might make it a bit easier to understand. maybe "to calculate the total L3 cache size, iterate over cache_info_list and add up the sizes of the L3 cache blocks with unique cache ID" or something like that? https://review.coreboot.org/c/coreboot/+/85640/comment/6e68e201_396243f4?us… : PS9, Line 59: } i'd add a newline here -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 20:38:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Add ALC1320 codec to devicetree
by Kapil Porwal (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Jayvik Desai, Mac Chiang, Pranava Y N, Subrata Banik, Weimin Wu. Kapil Porwal has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/86747?usp=email ) Change subject: mb/google/fatcat/var/felino: Add ALC1320 codec to devicetree ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/felino/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86747/comment/04f6160c_9808049c?us… : PS3, Line 221: 3.1 > I missed it. I think we should rebase on this CL https://review.coreboot. […] Yes. Please rebase. -- To view, visit https://review.coreboot.org/c/coreboot/+/86747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8763888810f56eb45523e3bcf7ef082900b1225 Gerrit-Change-Number: 86747 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mac Chiang <mac.chiang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 20:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mac Chiang <mac.chiang(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree
by Kapil Porwal (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Jayvik Desai, Mac Chiang, Paul Menzel, Pranava Y N, Varun Upadhyay, Weimin Wu. Kapil Porwal has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85572?usp=email ) Change subject: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Gerrit-Change-Number: 85572 Gerrit-PatchSet: 4 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 20:27:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Kapil Porwal (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Mac Chiang, Naveen M, Pranava Y N, Subrata Banik, Tongtong Pan, Varun Upadhyay, Weimin Wu. Kapil Porwal has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 4 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 20:26:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Felix Held (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Andy Ebrahiem, Angel Pons, Jincheng Li, Jérémy Compostella, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Shuo Liu. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/85638/comment/6d6b0168_30e471ab?us… : PS7, Line 215: bool __weak soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) hmm, i wonder if it would be better to have a kconfig option to replace the common implementation by a soc-specific one instead of having a weak function that gets overridden. in soc/amd we tried to minimize the usage of weak functions, since in the kconfig symbol case, mismatches result in linker errors instead of unexpected behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: NyeonWoo Kim Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 31 Mar 2025 19:55:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/glinda/psp_verstage/Makefile.mk: Fix incorrect syntax
by Angel Pons (Code Review) 31 Mar '25

31 Mar '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Martin L Roth, Maximilian Brune, Patrick Rudolph. Angel Pons has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86865?usp=email ) Change subject: soc/amd/glinda/psp_verstage/Makefile.mk: Fix incorrect syntax ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b Gerrit-Change-Number: 86865 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Mar 2025 19:34:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit March 2025